Abstract: Methods and systems are provided for analyzing cells of a cell library used to generate a layout. One exemplary method involves determining a routed connection location utilized in the layout for a pin of the cell for each instance of the cell in the layout. The method continues by determining a utilization metric for the pin of the cell based on the plurality of routed connection locations and a plurality of possible connection locations for the pin, and displaying the utilization metric on a display device.

Abstract: A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.

Abstract: A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.

Abstract: Methods and systems are provided for analyzing cells of a cell library used to generate a layout. One exemplary method involves determining a routed connection location utilized in the layout for a pin of the cell for each instance of the cell in the layout. The method continues by determining a utilization metric for the pin of the cell based on the plurality of routed connection locations and a plurality of possible connection locations for the pin, and displaying the utilization metric on a display device.

Abstract: A method and apparatus for determining instruction execution ordering in a data processing system (10). In one form, a control bit (52) is used by data processing system (10) to determine whether a standard instruction or a modified instruction is executed. The standard instruction performs a read bus cycle following by a write bus cycle. The bus (12) must be locked between the read and the write cycles in order to maintain coherency in semaphore applications. The modified instruction performs a buffered write bus cycle following by a read bus cycle. The bus (12) does not need to be locked between the write and the read cycles in order to maintain coherency in semaphore applications. Not locking the bus (12) can increase bus bandwidth in some bus systems.

Abstract: A data processing system (10) and method for performing a snoop-retry protocol using an arbiter (14). Multiple bus masters (12, 16, 17) are coupled to multiple shared buses (20, 22, 24, 26). Each bus master (12, 16, 17) may initiate a bus transaction ("initiating master"), or snoop the bus transaction ("snooping bus master") occurring on a shared bus (20). When an initiating processor requests access to a dirty cache line in a memory (18), a snooping bus master asserts a shared address retry (ARTRY*) signal to inform the initiating processor to relinquish ownership of the shared bus (20) and retry the bus transaction. Upon detecting the shared ARTRY* signal, all potential bus masters remove their bus requests and ignore any bus grants from the arbiter (14), thus allowing the snooping processor which asserted the ARTRY* signal to gain ownership of the shared bus (20) to perform the snoop copyback.

Abstract: A data processing system (10) and method for performing bus arbitration protocol using an arbiter (14). The data processing system (10) has multiple bus masters (12, 16) each of which is coupled to multiple shared buses (20, 22, 24, 28). The arbiter (14) detects a bus request from a requesting bus master, and responds with a bus grant to notify the requesting bus master that the arbiter has selected the requesting bus master to be a bus-master elect for a shared bus (20). The requesting bus master monitors a shared signal line to determine when a current bus master has released ownership of the shared bus (20). When the requesting bus master assumes ownership of the shared bus it deactivates the bus request signal for a dock period after commencement of the bus transaction, which allows the arbiter (14) to select a next bus master-elect, thereby preventing any bus master from monopolizing the shared bus (20).

Abstract: A first processing system is coupled to a plurality of integrated circuits along a P bus. Each of these integrated circuits has a combination cache and memory management unit (MMU). The cache/MMU integrated circuits are also connected to a main memory via an M bus. A second processing system is also coupled to the main memory primarily via a secondary bus but also via the M bus. External TAGs coupled between the M bus and the secondary bus are used to maintain coherency between the first and second processing systems. Each external TAG corresponds to a particular cache/MMU integrated circuit and maintains information as to the status of its corresponding cache/MMU integrated circuit. The cache/MMU integrated circuit provides the necessary status information to its corresponding external TAG in a very efficient manner. Each cache/MMU integrated circuit can also be converted to a SRAM mode in which the cache performs like a conventional high speed static random access memory (SRAM).