Abstract: A voltage regulator includes an error amplifier configured to amplify a difference between a feedback voltage and a reference voltage. The regulator also includes an N-type metal-oxide-semiconductor (NMOS) driver circuit. The driver circuit includes an n-type field effect transistor. The driver circuit is communicatively coupled to output of the error amplifier. The regulator further includes a feedback circuit communicatively coupled between the NMOS driver circuit and an input of the error amplifier to provide the feedback voltage.

Abstract: A voltage regulator includes an error amplifier configured to amplify a difference between a feedback voltage and a reference voltage. The regulator also includes an N-type metal-oxide-semiconductor (NMOS) driver circuit. The driver circuit includes an n-type field effect transistor. The driver circuit is communicatively coupled to output of the error amplifier. The regulator further includes a feedback circuit communicatively coupled between the NMOS driver circuit and an input of the error amplifier to provide the feedback voltage.

Abstract: The average of a complex waveform measured over a time period may be determined by first converting the complex waveform to a voltage, then converting this voltage to a current and using this current to charge a capacitor. At the end of the measurement time period the voltage charge (sample voltage) on the capacitor may be sampled by a sample and hold circuit associated with an analog-to-digital converter (ADC). Then the voltage charge on the sample capacitor may be removed, e.g., capacitor plates shorted by a dump switch in preparation for the next average of the complex waveform sample measurement cycle. The ADC then converts this sampled voltage charge to a digital representation thereof and a true average of the complex waveform may be determined, e.g., calculated therefrom in combination with the measurement time period.

Abstract: An integrated circuit having a plurality of selectable modes, functions and/or characteristics may be configured at the time of product manufacture by providing an appropriate resistance value pull-up resistor at an external connection (pin) of the integrated circuit package. At least one external connection (pin) may be used for such configuration of the integrated circuit. This is done without having to program the integrated circuit before placing on the product printed circuit board. The same integrated circuit may thus be used for a plurality of different products without requiring any pre-programming thereof. The integrated circuit's personality (desired characteristics) will be programmed automatically as soon as power is first applied to the finished product printed circuit board. Once the integrated circuit has been configured at power up, the external at least one connection (pin), initially used for configuration, can be used for either analog or digital input, output or input/output.

Abstract: The average of a complex waveform measured over a time period may be determined by first converting the complex waveform to a voltage, then converting this voltage to a current and using this current to charge a capacitor. At the end of the measurement time period the voltage charge (sample voltage) on the capacitor may be sampled by a sample and hold circuit associated with an analog-to-digital converter (ADC). Then the voltage charge on the sample capacitor may be removed, e.g., capacitor plates shorted by a dump switch in preparation for the next average of the complex waveform sample measurement cycle. The ADC then converts this sampled voltage charge to a digital representation thereof and a true average of the complex waveform may be determined, e.g., calculated therefrom in combination with the measurement time period.

Abstract: A microcontroller has a programmable timebase, wherein the timebase has a trigger input to start a timer or counter of the timebase and wherein the timebase can be configured to operate upon receiving a trigger signal in a first mode to generate a plurality of timer/counter event signals until a reset bit in a control register is set and in a second mode to generate a single timer/counter event signal and wherein the timebase can be configured to operate in a third mode to generate a predefined number of timer/counter event signals, wherein the predefined number is defined by a plurality of bits of a register.

Abstract: A fluorescent lamp light intensity dimming control generates a pulse width modulation (PWM) signal at about a fifty percent duty cycle and has very fine frequency change granularity to allow precise and smooth light dimming capabilities. Intermediate PWM signal frequencies between the frequencies that are normally generated from values in a period register of the PWM generator are provided with a variable frequency clock source to the PWM generator. Selection of each frequency from the plurality of frequencies available from the variable frequency clock source may be determined from a value stored in a variable frequency clock register. A microcontroller may be used to select appropriate frequencies for dimming control of the fluorescent lamp from the variable frequency clock source, and the period and duty cycle values used in generating the PWM signal at about a fifty percent duty cycle.

Abstract: A fluorescent lamp light intensity dimming control generates a pulse width modulation (PWM) signal at about a fifty percent duty cycle and has very fine frequency change granularity to allow precise and smooth light dimming capabilities. Intermediate PWM signal frequencies between the frequencies that are normally generated from values in a period register of the PWM generator are provided with a variable frequency clock source to the PWM generator. Selection of each frequency from the plurality of frequencies available from the variable frequency clock source may be determined from a value stored in a variable frequency clock register. A microcontroller may be used to select appropriate frequencies for dimming control of the fluorescent lamp from the variable frequency clock source, and the period and duty cycle values used in generating the PWM signal at about a fifty percent duty cycle.

Abstract: A method of filtering one or more input signals, includes receiving one or more input signals, each having an input signal value. The method includes storing at least two instructions in a program memory to filter one or more of the input signals. Each instruction includes an opcode and identifies at least two input locations and at least one output location. The method includes, for one or more of the one or more input signals, and then for each instruction, fetching input values from the at least two input locations. The method further includes performing an operation on the input values to produce an output value, based on the opcode of the instruction and outputting the output value to at least one output location.

Abstract: Capture and monitoring of critical data from a microcontroller is performed without halting or changing normal program execution therein. Data is captured according to stored program addresses that may run in the background during operation of the microcontroller. When an address match occurs data may thereby be captured. The captured data may be output via an in-circuit debugger (ICD) interface to a workstation computer. Therefore, a program emulator is no longer necessary for program evaluation and debugging purposes.

Abstract: A CAN module comprises a buffer memory comprising a data and address input and a plurality of addressable buffers, a data receive register being coupled with the buffer memory receiving data from a serial data stream, a filter register, a comparator comparing the filter register value with an identifier transmitted in the serial data stream generating an acceptance signal, a buffer pointer coupled with the comparator to receive the acceptance signal, and an address register receiving an address from the buffer pointer for addressing the buffer memory. The arrangement can dynamically assign any filter register to any buffer within the buffer memory.

Abstract: A CAN module comprising a buffer memory comprising a data and address input and a plurality of addressable buffers, a data receive register being coupled with the buffer memory receiving data from a serial data stream, a filter register, a comparator comparing the filter register value with an identifier transmitted in the serial data stream generating an acceptance signal, a buffer pointer coupled with the comparator to receive said acceptance signal, and a multiple function address register unit comprising a first mode in which the unit receives an address from the buffer pointer for addressing the buffer memory and a second mode in which the acceptance signal is coupled with an incrementer within the multiple function address register unit wherein the incrementer increments the address register upon generation of the acceptance signal. The arrangement can be switched between two modes. The module operates in a first mode and dynamically assigns any filter register to any buffer within the buffer memory.

Abstract: A CAN module comprising a buffer memory comprising a data and address input and a plurality of addressable buffers, a data receive register being coupled with the buffer memory receiving data from a serial data stream, a filter register, a comparator comparing the filter register value with an identifier transmitted in the serial data stream generating an acceptance signal, a buffer pointer coupled with the comparator to receive said acceptance signal, and a multiple function address register unit comprising a first mode in which the unit receives an address from the buffer pointer for addressing the buffer memory and a second mode in which the acceptance signal is coupled with an incrementer within the multiple function address register unit wherein the incrementer increments the address register upon generation of the acceptance signal. The arrangement can be switched between two modes. The module operates in a first mode and dynamically assigns any filter register to any buffer within the buffer memory.

Abstract: A CAN module comprises a buffer memory comprising a data and address input and a plurality of addressable buffers, a data receive register being coupled with the buffer memory receiving data from a serial data stream, a filter register, a comparator comparing the filter register value with an identifier transmitted in the serial data stream generating an acceptance signal, a buffer pointer coupled with the comparator to receive the acceptance signal, and an address register receiving an address from the buffer pointer for addressing the buffer memory. The arrangement can dynamically assign any filter register to any buffer within the buffer memory.