Patents by Inventor James Bonanno
James Bonanno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11928471Abstract: Embodiments for a metadata predictor. An index pipeline generates indices in an index buffer in which the indices are used for reading out a memory device. A prediction cache is populated with metadata of instructions read from the memory device. A prediction pipeline generates a prediction using the metadata of the instructions from the prediction cache, the populating of the prediction cache with the metadata of the instructions being performed asynchronously to the operating of the prediction pipeline.Type: GrantFiled: August 19, 2021Date of Patent: March 12, 2024Assignee: International Business Machines CorporationInventors: Edward Thomas Malley, Adam Benjamin Collura, Brian Robert Prasky, James Bonanno, Dominic Ditomaso
-
Patent number: 11868779Abstract: Aspects of the invention include a computer-implemented method of updating metadata prediction tables. The computer-implemented method includes establishing, in the metadata prediction tables, a prediction of how a set of instructions will resolve and identifying that the set of instructions is completed. The computer-implemented method also includes determining, upon completion of the set of instructions, whether prediction update queues (PUQs) associated with the set of instructions indicate that the set of instructions resolved in one of a plurality of prescribed manners relative to the prediction and deciding that the metadata predictions tables are candidates to be updated based on the PUQs indicating that the set of instructions resolved in one of the plurality of prescribed manners.Type: GrantFiled: September 9, 2021Date of Patent: January 9, 2024Assignee: International Business Machines CorporationInventors: James Raymond Cuffney, Adam Benjamin Collura, James Bonanno, Brian Robert Prasky, Edward Thomas Malley, Suman Amugothu
-
Patent number: 11782919Abstract: Embodiments are provided for using metadata presence information to determine when to access a higher-level metadata table. It is determined that an incomplete hit occurred for a line of metadata in a lower-level structure of a processor, the lower-level structure being coupled to a higher-level structure in a hierarchy. It is determined that metadata presence information in a metadata presence table is a match to the line of metadata from the lower-level structure. Responsive to determining the match, it is determined to avoid accessing the higher-level structure of the processor.Type: GrantFiled: August 19, 2021Date of Patent: October 10, 2023Assignee: International Business Machines CorporationInventors: Adam Benjamin Collura, James Bonanno, Brian Robert Prasky
-
Publication number: 20230305850Abstract: A method of branch prediction in a processor includes: obtaining, by the processor, a branch instruction for which a direction of a branch is to be predicted; generating, by the processor, an index based on an instruction address, a global path vector (GPV), and a counter; selecting, by the processor, an entry from a data structure using the index; and predicting, by the processor, the direction of the branch using information included in the selected entry. The method may include modifying a tag in the selected entry based at least in part on another GPV.Type: ApplicationFiled: March 24, 2022Publication date: September 28, 2023Inventors: Brian Robert Prasky, James Bonanno, Adam Benjamin Collura, Edward Thomas Malley, Deepankar Bhattacharjee
-
Patent number: 11663126Abstract: Embodiments include storing return addresses for a branch-target-buffer. Aspects include receiving a first instruction and based on a determination that the first instruction is a branch instruction and potentially a call, storing a return address associated with the branch instruction in a prediction return address table, wherein the prediction return address table includes an entry that corresponds to an index value that is created based on a target address of the first instruction, and wherein the entry includes the return address that is created based on an address of a sequential instruction of the first instruction. Aspects also include receiving a second instruction and based on a determination that the second instruction is predicted to be a return instruction with a predicted return address table index value from the branch-target-buffer, using the index value to select the return address to predict as the target address.Type: GrantFiled: February 23, 2022Date of Patent: May 30, 2023Assignee: International Business Machines CorporationInventors: James Bonanno, Brian Robert Prasky, Adam Benjamin Collura, Edward Thomas Malley, James Raymond Cuffney, Dominic Ditomaso
-
Publication number: 20230075992Abstract: Aspects of the invention include a computer-implemented method of updating metadata prediction tables. The computer-implemented method includes establishing, in the metadata prediction tables, a prediction of how a set of instructions will resolve and identifying that the set of instructions is completed. The computer-implemented method also includes determining, upon completion of the set of instructions, whether prediction update queues (PUQs) associated with the set of instructions indicate that the set of instructions resolved in one of a plurality of proscribed manners relative to the prediction and deciding that the metadata predictions tables are candidates to be updated based on the PUQs indicating that the set of instructions resolved in one of the plurality of proscribed manners.Type: ApplicationFiled: September 9, 2021Publication date: March 9, 2023Inventors: James Raymond Cuffney, Adam Benjamin Collura, James Bonanno, Brian Robert Prasky, Edward Thomas Malley, Suman Amugothu
-
Publication number: 20230057600Abstract: Embodiments for a metadata predictor. An index pipeline generates indices in an index buffer in which the indices are used for reading out a memory device. A prediction cache is populated with metadata of instructions read from the memory device. A prediction pipeline generates a prediction using the metadata of the instructions from the prediction cache, the populating of the prediction cache with the metadata of the instructions being performed asynchronously to the operating of the prediction pipeline.Type: ApplicationFiled: August 19, 2021Publication date: February 23, 2023Inventors: Edward Thomas MALLEY, Adam Benjamin COLLURA, Brian Robert PRASKY, James BONANNO, Dominic DITOMASO
-
Publication number: 20230053733Abstract: Embodiments are provided for using metadata presence information to determine when to access a higher-level metadata table. It is determined that an incomplete hit occurred for a line of metadata in a lower-level structure of a processor, the lower-level structure being coupled to a higher-level structure in a hierarchy. It is determined that metadata presence information in a metadata presence table is a match to the line of metadata from the lower-level structure. Responsive to determining the match, it is determined to avoid accessing the higher-level structure of the processor.Type: ApplicationFiled: August 19, 2021Publication date: February 23, 2023Inventors: Adam Benjamin Collura, JAMES BONANNO, Brian Robert Prasky
-
Publication number: 20230060033Abstract: Embodiments include a hierarchical metadata prediction system that includes a first line-based predictor having a first line for storage of metadata entries, and a second line-based predictor configured to store metadata entries from the first line-based predictor. The second line-based predictor has a second line, the second line including a plurality of containers, the plurality of containers including at least a first set of containers having a first size and a second set of containers having a second size. The system also includes a processing device configured to transfer one or more metadata entries between the first line-based predictor and the second-line based predictor. Embodiments also include a computer-implemented method and a computer program product.Type: ApplicationFiled: August 20, 2021Publication date: February 23, 2023Inventors: Brian Robert Prasky, James Bonanno, Adam Benjamin Collura
-
Patent number: 11556474Abstract: Embodiments are provided for an integrated semi-inclusive hierarchical metadata predictor. A hit in a second-level structure is determined, the hit being associated with a line of metadata in the second-level structure. Responsive to determining that a victim line of metadata in a first-level structure meets at least one condition, the victim line of metadata is stored in the second-level structure. The line of metadata from the second-level structure is stored in a first-level structure to be utilized to facilitate performance of a processor, the line of metadata from the second-level structure including entries for a plurality of instructions.Type: GrantFiled: August 19, 2021Date of Patent: January 17, 2023Assignee: International Business Machines CorporationInventors: James Bonanno, Adam Benjamin Collura, Edward Thomas Malley, Brian Robert Prasky
-
Patent number: 11509164Abstract: Systems and methods are provided for solar energy management that can charge a battery from a solar panel as well as operate without a battery, using the same equipment. This multi-modal functionality provides the ability to incrementally increase capacity and extend the availability of electricity from daytime-only to a continuous supply irrespective of solar conditions.Type: GrantFiled: September 23, 2020Date of Patent: November 22, 2022Assignee: Solar Seed LLCInventors: R. David Gibbs, C. James Bonanno, Jr.
-
Patent number: 11243774Abstract: Methods, systems and computer program products for dynamically selecting an OSC hazard avoidance mechanism are provided. Aspects include receiving a load instruction that is associated with an operand store compare (OSC) prediction. The OSC prediction is stored in an entry of an OSC history table (OHT) and includes a multiple dependencies indicator (MDI). Responsive to determining the MDI is in a first state, aspects include applying a first OSC hazard avoidance mechanism in relation to the load instruction. Responsive to determining that the load instruction is dependent on more than one store instruction, aspects include placing the MDI in a second state. The MDI being in the second state provides an indication to apply a second OSC hazard avoidance mechanism in relation to the load instruction.Type: GrantFiled: March 20, 2019Date of Patent: February 8, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Raymond Cuffney, Adam Collura, James Bonanno, Edward Malley, Anthony Saporito, Jang-Soo Lee, Michael Cadigan, Jr., Jonathan Hsieh
-
Patent number: 11182165Abstract: A system includes a branch predictor and a processing circuit configured to perform a plurality of operations including storing a skip-over offset value in the branch predictor. The skip-over offset value defines a number of search addresses of the branch predictor to be skipped. The operations further include searching the branch predictor for a branch prediction. Responsive to finding the branch prediction, the searching of the branch predictor is re-indexed based on the skip-over offset value associated with the branch prediction.Type: GrantFiled: November 19, 2018Date of Patent: November 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Bonanno, Daniel Lipetz, Brian Robert Prasky, Anthony Saporito, Adam Collura, Steven J. Hnatko
-
Patent number: 11163573Abstract: A system includes a hierarchical metadata predictor and a processing circuit. The hierarchical metadata predictor includes a first-level metadata predictor and a second-level metadata predictor. The processing circuit is configured to perform a plurality of operations including storing new or updated metadata into the first-level metadata predictor and searching the first-level metadata predictor for a metadata prediction. Responsive to finding the metadata prediction in the first-level metadata predictor, the metadata prediction is output corresponding to an entry of the first-level metadata predictor that is a hit. One or more entries of the first-level metadata predictor that are non-hits are periodically written to the second-level metadata predictor. The first-level metadata predictor is updated based on locating the metadata prediction in the second-level metadata predictor.Type: GrantFiled: February 13, 2019Date of Patent: November 2, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Bonanno, Varnika Atmakuri, Adam Collura, Brian Robert Prasky, Anthony Saporito, Suman Amugothu
-
Patent number: 11144321Abstract: Examples of techniques for store hit multiple load side register for operand store compare are described herein. An aspect includes, based on detecting a store hit multiple load condition in the processor, updating a register of the processor to hold information corresponding to a first store instruction that triggered the detected store hit multiple load condition. Another aspect includes, based on issuing a second store instruction in the processor, determining whether the second store instruction corresponds to the information in the register. Another aspect includes, based on determining that the second store instruction corresponds to the information in the register, tagging the second store instruction with an operand store compare mark.Type: GrantFiled: February 20, 2019Date of Patent: October 12, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yair Fried, Jonathan Hsieh, Eyal Naor, James Bonanno, Gregory William Alexander
-
Patent number: 10990405Abstract: A computer system includes a branch detection module and a branch predictor module. The branch detection module determines that a first program branch is a possible call branch having a next sequential instruction address (NSIA), and determines that a first routine branch is a possible return capable branch having the first routine instruction address that is a detected as being offset. The branch predictor module determines that a second program branch is a possible call branch having a next sequential instruction address (NSIA), and determines that a second routine branch is a predicted return branch having a predicted target instruction address based on the NSIA of the second program branch and the predicted offset.Type: GrantFiled: February 19, 2019Date of Patent: April 27, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Adam Collura, James Bonanno, Steven J. Hnatko, Brian Robert Prasky, Daniel Lipetz
-
Patent number: 10977040Abstract: Methods, systems and computer program products for heuristically invalidating non-useful entries in an array are provided. Aspects include receiving an instruction that is associated with an operand store compare (OSC) prediction for at least one of a store function and a load function. The OSC prediction is stored in an entry of an OSC history table (OHT). Aspects also include executing the instruction. Responsive to determining, based on the execution of the instruction, that data forwarding did not occur, aspects include incrementing a useless OSC prediction counter. Responsive to determining that the useless OSC prediction counter is equal to a predetermined value, aspects also include invalidating the entry of the OHT associated with the instruction.Type: GrantFiled: February 19, 2019Date of Patent: April 13, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Raymond Cuffney, Adam Collura, James Bonanno, Jang-Soo Lee, Eyal Naor, Yair Fried, Brian Robert Prasky
-
Publication number: 20210091593Abstract: Systems and methods are provided for solar energy management that can charge a battery from a solar panel as well as operate without a battery, using the same equipment. This multi-modal functionality provides the ability to incrementally increase capacity and extend the availability of electricity from daytime-only to a continuous supply irrespective of solar conditions.Type: ApplicationFiled: September 23, 2020Publication date: March 25, 2021Inventors: R. David Gibbs, C. James Bonanno, JR.
-
Patent number: 10929142Abstract: Provided are embodiments including a computer-implemented method, system and computer program product for determining precise operand-store-compare (OSC) predictions to avoid false dependencies. Some embodiments include detecting an instruction causing an OSC event, wherein the OSC event is at least one of a store-hit-load event or a load-hit-store event, marking an entry in a queue for the instruction based on the detected OSC event, wherein marking the entry comprises setting a bit and saving a tag in the entry in the queue. Some embodiments also include installing an address for the instruction and the tag in the history table responsive to completing the instruction.Type: GrantFiled: March 20, 2019Date of Patent: February 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gregory William Alexander, James Bonanno, Adam Collura, James Raymond Cuffney, Yair Fried, Jonathan Hsieh, Jang-Soo Lee, Edward Malley, Anthony Saporito, Eyal Naor
-
Patent number: 10838659Abstract: Examples of techniques for controlling write requests to a memory structure having limited write ports are described herein. An aspect includes storing, in a first queue, write requests received from a first source having a first priority. Another aspect includes storing, in a second queue, write requests received from a second source having a second priority, wherein the second priority is lower than the first priority. Aspects also include identifying a selected queue from the first queue and the second queue based on a selection algorithm, which is a function of a state associated with the first queue and the second queue. Aspects further include forwarding a write request from the selected queue to a write port of the memory structure.Type: GrantFiled: February 8, 2019Date of Patent: November 17, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Varnika Atmakuri, Adam Collura, James Bonanno, Suman Amugothu