Abstract: A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with a bistable sense amplifier circuit of the dynamic type at the center of each column. A dummy cell is connected to each column line half and is addressed when a memory cell on the opposite side of the sense amplifier is addressed by one of the row lines. A coupling transistor connects each column line half to one of the cross-coupled driver transistors of the bistable circuit. The coupling transistors are of the depletion mode type and each has its gate connected to the sense node on the opposite side between the other coupling transistor and driver transistor.