Abstract: A method of forming a multilayer circuit board is disclosed which includes a build-up process in which, beginning with a solidified layer of the dielectric disposed upon a substrate, alternate layers of conducting metal and dielectric are sequentially deposited. Each layer of conducting metal lines is defined using photoresist and a photolithographic technique. After the lines are deposited, the photoresist is removed and a second layer of photoresist defines the conductive posts which function as through holes between metal layers. After each layer of conductive line and posts is formed, and the photoresist is removed, the dielectric is flowed into place and solidified to insulate adjacent metal lines and posts. The process may be repeated as many times as necessary to build up layers of conducting metal and dielectric, and form the completed multilayer wiring board.

Abstract: A very fine line three-dimensional package is constructed without lamination during construction of the signal core. Construction of the signal core employs a method of line and hole formation and planarization without drilling, and avoids imposing excessive stress on the package during its assembly. In forming the three-dimensional structure, a power core which may comprise a single or multiple layers is manufactured in the conventional method using a very high dielectric constant material.A signal core is on both sides of the power core, using a sequential approach with a low dielectric constant material. The method comprises utilizing photoresist techniques to define the regions of horizontal lines running parallel to the surface of the power core substrate and vertical posts running perpendicular to the surface of the power core, as each layer of lines and posts is established.

Abstract: A semiconductor mounting system is provided for the detachable surface mounting of one or more semiconductor dies on a conductor substrate, such as a ceramic substrate or printed circuit board. The system employs a resilient, anisotropic conductor pad which is interposed between the semiconductor die and the conductor substrate. The conductor pad is capable of conducting electric signals in one direction only, and insulates in the other two orthogonal directions. Thus, by compressing the semiconductor die and resilient conductor pad against the conductor substrate, electrical contact is established between contacts on the semiconductor die and corresponding contacts on the conductor substrate. In the preferred embodiment, additional conductor pads are placed over the semiconductor dies, and a heat sink placed over the second conductor pads.

Abstract: Electronic assemblies are fabricated by stacking alternate connecting layers and component layers. The component layers may be virtually any rigid structure having contact regions formed on at least one face thereof. The connecting layers are formed from anisotropic elastomeric conductors which in turn are fabricated by stacking a plurality of conductive sheets and insulating sheets, where the conductive sheets have a plurality of parallel electrically conductive elements formed therein. By introducing a curable elastomeric resin into the stacked structure so formed, and then curing the elastomer, a solid elastomeric block having a plurality of parallel electrically conductive elements running its length is obtained. Individual elastomeric conductors suitable as connecting layers interfacing between adjacent component layers are obtained by slicing the block in a direction perpendicular to the conductors.

Abstract: An anisotropic elastomeric conductor is fabricated by stacking a plurality of metal sheets and elastomeric sheets, where the metal sheets have a plurality of parallel electrically conductive elements formed therein. By coating a curable elastomeric resin on the metal sheets, and then curing the resulting layered structure, a solid elastomeric block having a plurality of parallel electrically conductive elements running its length is obtained. Individual elastomeric conductors suitable for interfacing between electronic components are obtained by slicing the block in a direction perpendicular to the conductors. The conductor slices so obtained are particularly suitable for interfacing between electronic devices having planar arrays of electrical contact pads.

Abstract: A multiple chip interconnection system and package for interconnecting and cooling integrated circuits includes an electrically-conductive plate 10 having an upper surface 12. On the upper surface 12, a first layer of polyimide 16 or other electrically-insulating material is deposited. One or more layers of electrical interconnections 17, 18, 21, 22, and insulating material 19, 24, are then disposed on the insulating material 16 to provide a network of electrical connections embedded in insulating material, yet which is sufficiently thin to offer minimal thermal resistance to the transfer of heat from integrated circuits mounted thereon to the plate 10. After the layers of interconnections are completed, one or more conductive planes are deposited across the interconnections to serve as a mounting surface for the integrated circuits and to distribute power and ground signals as necessary.

Abstract: A module for a semiconductor chip having a front face with a two dimensional array of power, ground and signal contacts is disclosed. Power, ground and signal conductors extend from the respective contacts on the front face of the chip. A pair of electrically conductive plates are parallel to the front face of the chip and located at the termination of the conductors. The plate nearer the conductors is electrically coupled to either the power or ground conductors, and contains apertures corresponding to the remaining ground or power conductors and to the signal conductors. A plurality of discrete signal transmission members are located at a surface of the plate farther from the conductors. The ground or power conductors not connected to the near plate are electrically coupled to the far plate through certain of the apertures, and the signal conductors are coupled to the respective signal transmission members through the remaining apertures.

Abstract: A semiconductor chip module for a semiconductor chip having an exposed front face with a two dimensional array of contacts is disclosed. A connector plate is located proximate the front face of the chip. The connector plate has a plurality of apertures which correspond to and are aligned with the contacts of the semiconductor chip. A plurality of transmission elements are located proximate the connector plate opposite from the semiconductor chip. A plurality of flexible conductors extend through the respective apertures of the connector plate. The flexible conductors are electrically coupled to the contacts of the chip and to the transmission elements.

Abstract: A mounting arrangement for a semiconductor integrated circuit chip having a first heat sink mounted to the bottom surface of the chip in good heat transfer relation and a second heat sink mounted to a region of the top surface of the chip interior to the bonding pads.

Abstract: A module for a semiconductor chip is disclosed. The module includes a heat sink with a flat surface to which the back face of the semiconductor chip is directly bonded. The exposed face of the chip has an array of power, ground and signal contacts. A plurality of alternating power and ground bus bars span the exposed face of the chip. A multilayer ceramic is located on the other side of the bus bar array and has a surface proximate the power and ground bus bars with an array of contacts which correspond to at least the signal contacts on the chip. Power leads connect the power bus bars to adjacent power contacts on the chip; ground leads connect the ground bus bars to adjacent ground contacts on the chip; and signal leads pass between adjacent power and ground bus bars and interconnect the signal contacts on the chip with the corresponding signal contacts on the ceramic.

Abstract: A semiconductor chip having a two-dimensional array of contacts on an exposed face thereof is mounted in a semiconductor chip module. A mechanism for delivering electricity spans the exposed face of the chip to which it is connected and includes interstitial gaps. A conductor board has a surface proximate the electricity delivering mechanism opposite from the chip. The surface of the board has a two-dimensional array of contacts which correspond to at least some of the contacts on the chip. A biasing mechanism extends from the electricity delivering mechanism toward the exposed face of the semiconductor chip and toward the conductor board, and corresponds to the array of contacts on the chip and board. Signal leads pass through the interstitial gaps and have end portions which extend transversely over the biasing means. The end portions of the signal leads are biased against the contacts of the chips and board by the biasing mechanism.

Abstract: A semiconductor package and electronic array in which the semiconductor packages of the array share a common substrate. The substrate has a plurality of sets of contacts with each set of contacts receiving contacts of a semiconductor chip. Each chip and set of contacts is surrounded by a closed length of bond receptive material. A heat dissipation member is attached to each chip by means of a heat conductive plate, and an annular ring is bonded to each heat dissipation member and to the closed length of bond receptive material to hermetically seal the chip.

Abstract: A leadless package receptacle for mounting and interconnecting to electronic devices (e.g. leadless package) which can be interconnected with a second receptacle for packaging such devices, said receptacles having improved spring contact members. The receptacle incorporates a plurality of uniquely designed spring contacts for connection to a printed circuit board or other circuit member in a conventional manner. The spring contacts are arranged and configured within the receptacle to yieldably engage the lower surface of the leadless package so as to maintain a line contact. In addition, each spring member has a separate arm member to engage the spring contact members of the second package. The leadless package includes a chip carrier which has a plurality of conductive areas on the lower surface thereof for engaging the spring contacts. Edge regions are cooperatively disposed on the carrier with respect to locking members on the receptacle for retaining the package in the receptacle.

Abstract: A leadless package receptacle for packaging and mounting electronic devices. The receptacle retains a plurality of spring contacts for soldering to a printed circuit board in a conventional manner and disposed within the receptacle to yieldably engage the lower surface of the package. The chip carrier has a plurality of conductive areas on the lower surface thereof for engaging the spring contacts and further has edge regions cooperatively disposed with respect to locking members on the receptacle for retaining the package in the receptacle. A mounting and removal tool is also disclosed.