Patents by Inventor James Cady
James Cady has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050280135Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention, two CSPs are stacked, with one CSP disposed above the other. The two CSPs are connected with flex circuitry. A form standard is disposed between the flex circuitry and a CSP in the stack. The form standard can take many configurations and may be used where flex circuits are used to connect CSPs to one another in stacked modules having two or more constituent CSPs. For example, in stacked modules that include four CSPs, three form standards are employed in preferred embodiments, although fewer may be used. The form standard provides a thermally conductive physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design.Type: ApplicationFiled: August 4, 2005Publication date: December 22, 2005Inventors: Russell Rapport, James Cady, James Wilder, David Roper, James Wehrly, Jeff Buchle, Julian Dowden
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Publication number: 20050263872Abstract: A form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design that is disposed about the form. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance.Type: ApplicationFiled: July 1, 2005Publication date: December 1, 2005Inventors: James Cady, James Wilder, David Roper, James Wehrly
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Publication number: 20050146031Abstract: The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.Type: ApplicationFiled: December 14, 2004Publication date: July 7, 2005Inventors: Julian Partridge, James Cady, James Wilder, David Roper, James Wehrly
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Publication number: 20050146011Abstract: The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and its application environment. The module has a bailout pattern with a different pitch and/or supplemental module contacts devised to allow combined signaling to the integrated circuits through contacts having a desired bailout footprint.Type: ApplicationFiled: March 8, 2005Publication date: July 7, 2005Inventors: David Roper, James Cady, James Wilder, James Wehrly, Jeff Buchle, Julian Dowden
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Publication number: 20050067683Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance.Type: ApplicationFiled: October 29, 2004Publication date: March 31, 2005Inventors: Russell Rapport, James Cady, James Wilder, David Roper, James Wehrly, Jeff Buchle
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Publication number: 20050062144Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance.Type: ApplicationFiled: October 12, 2004Publication date: March 24, 2005Inventors: Russell Rapport, James Cady, James Wilder, David Roper, James Wehrly, Jeff Buchle
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Publication number: 20050057911Abstract: The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.Type: ApplicationFiled: March 19, 2004Publication date: March 17, 2005Inventors: Russell Rapport, James Cady, James Wilder, David Roper, James Wehrly, Jeff Buchle
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Publication number: 20050056921Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or more conductive layers with preferred embodiments having two conductive layers. A form standard is disposed along the lower planar surface and extends laterally beyond the package of one or more CSPs in a stacked module. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be comprised of heat conductive material such as copper, for example.Type: ApplicationFiled: May 13, 2004Publication date: March 17, 2005Inventors: James Wehrly, James Cady, Julian Partridge, David Roper
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Publication number: 20050041402Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP integrated circuit and a support element CSP integrated circuit are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements. A portion of the flex circuit connected to the support element is folded over the base element to dispose the support element above the base element while reducing the overall footprint. The flex circuit provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB).Type: ApplicationFiled: October 5, 2004Publication date: February 24, 2005Inventors: James Cady, James Wilder, David Roper, Russell Rapport, James Wehrly, Jeffrey Buchle
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Publication number: 20050041403Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP integrated circuit and a support element CSP integrated circuit are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements. A portion of the flex circuit connected to the support element is folded over the base element to dispose the support element above the base element while reducing the overall footprint. The flex circuit provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB).Type: ApplicationFiled: October 5, 2004Publication date: February 24, 2005Inventors: James Cady, James Wilder, David Roper, Russell Rapport, James Wehrly, Jeffrey Buchle
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Publication number: 20050041404Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The invention provides techniques and structures for aggregating chip scale-packaged integrated circuits (CSPs) or leaded packages with other CSPs or with monolithic or stacked leaded packages into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP and a support element CSP are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements.Type: ApplicationFiled: October 5, 2004Publication date: February 24, 2005Inventors: James Cady, James Wilder, David Roper, Russell Rapport, James Wehrly, Jeffrey Buchle
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Publication number: 20050018412Abstract: The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and its application environment. The module has a ballout pattern with a different pitch and/or supplemental module contacts devised to allow combined signaling to the integrated circuits through contacts having a desired ballout footprint.Type: ApplicationFiled: August 9, 2004Publication date: January 27, 2005Inventors: David Roper, James Cady, James Wilder, James Wehrly, Jeff Buchle, Julian Dowden
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Publication number: 20050009234Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. Multiple numbers of CSPs may be stacked in accordance with the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. A form standard is disposed along a planar surface of a CSP. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. The form standard achieves a reduced profile after the CSP has been attached to the form standard. In addition, in constructing modules in accordance with some preferred modes of the invention, CSP contacts are reduced in height to create lower profile modules. Thus, low profile embodiments of the modules of the present invention are devised.Type: ApplicationFiled: August 6, 2004Publication date: January 13, 2005Inventors: Julian Partridge, James Wehrly, Julian Dowden, David Roper, James Cady
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Patent number: 6618257Abstract: Provided is a system and method for selectively stacking and interconnecting integrated circuit devices having a data path of n-bits to create a high-density integrated circuit module having a data path of greater than n-bits. Integrated circuits are vertically stacked one above the other. Where the constituent IC elements have a data path of n-bits in width, a module devised in accordance with a preferred embodiment of the present invention presents a data path 2n-bits wide. In a preferred embodiment, an interconnection frame comprised of printed circuit board material is disposed about two similarly oriented ICs to provide interconnectivity of the constituent ICs and concatenation of their respective data paths. An array of clip-leads or other connectors are appended to module connection pads to provide lead-like structures for connection of the module to its operating environment.Type: GrantFiled: July 27, 2001Date of Patent: September 9, 2003Assignee: Staktek Group, L.P.Inventors: James Cady, David L. Roper, James G. Wilder, Julian Dowden, Jeff Buchle