Abstract: An apparatus for storing electrical energy is provided. The apparatus includes a first magnetic layer, a second magnetic layer, and a dielectric layer. The first magnetic layer has a first surface with saw tooth roughness; the second magnetic layer has a second surface with saw tooth roughness; and the dielectric layer is configured between the first magnetic layer and the second magnetic layer. The dielectric layer is arranged to store electrical energy; the first magnetic layer and the second magnetic layer are arranged to prevent electrical energy leakage; and the saw tooth roughness on the first surface and the second surface is designed to increase the capacitance of the apparatus.

Abstract: A conductive plug located in a planar dielectric layer, under GMR memory cells, are used to directly connect the lower ferromagnetic layer of one of the GMR memory cell and a conductive layer under the planar dielectric layer.

Abstract: A giant magnetoresistance (GMR) pad on the same level of GMR memory bit layer is used as an intermediate connection for plugs between the GMR pad and an underlying diffusion metal layer. A single large power metal plug is used to connect the GMR pad and the overlying power plane metal.

Abstract: A parallel plate magnetic capacitor (Mcap) includes two first pillar electrodes, two second pillar electrodes and a dielectric layer. The two first pillar electrodes electro-connect with each other and are located at right corner of a first plane and left corner of a second plane respectively. The two second pillar electrodes electro-connect with each other and are located at left corner of the first plane and right corner of the second plane respectively. The dielectric layer is located between the first pillar electrodes and the second pillar electrodes, such that the first pillar electrodes and the second pillar electrodes form capacitances therebetween.

Abstract: An integrated circuit with magnetic memory has a silicon transistor layer, at least one magnetic memory layer, and a metal routing layer. The silicon transistor layer is arranged to generate several logic operation functions. The magnetic memory layer is arranged to store the data required by the logic operation functions. The metal routing layer has several conducting lines to transmit the data between the silicon transistor layer and the magnetic memory layer.

Abstract: A DRAM cell includes a substrate, a transistor, and a magnetic capacitor. The substrate is composed of semiconductor material with a main surface, the transistor is formed at the main surface, and the magnetic capacitor is formed in a metal layer. The transistor includes a source region and a drain region formed at the main surface of the substrate. The transistor also includes a control gate placed between the source region and the drain region, and separated from the substrate by a thin control dielectric. The magnetic capacitor includes a first electrode layer, a dielectric layer formed on the surface of the first electrode layer, and a second electrode layer formed on the surface of the dielectric layer. The DRAM cell increases the density, simplifies the manufacturing process, and reduces or eliminates the refresh rate. A DRAM cell with the magnetic capacitor formed in multiple layers is also provided.

Abstract: A DRAM cell includes a substrate, a transistor, and a capacitor. The substrate is composed of semiconductor material with a main surface, the transistor is formed at the main surface, and the capacitor is formed in a metal layer. The transistor includes a source region and a drain region formed at the main surface of the substrate. The transistor also includes a control gate placed between the source region and the drain region, and separated from the substrate by a thin control dielectric. The capacitor includes a first electrode layer, a dielectric layer formed on the surface of the first electrode layer, and a second electrode layer formed on the surface of the dielectric layer. The DRAM cell increases the density and simplifies the manufacturing process. A DRAM cell with the capacitor formed in multiple layers is also provided.

Abstract: An electronics system module is provided. The electronics system module includes an electronics device and a power source. The power source includes a capacitor coupling to the electronics device and providing power thereto and an adjustable resistance connected in series between the capacitor and the electronics device. The resistance is adjusted by a control mechanism, so that the voltage supplied to the electronics device from the capacitor is constant.

Abstract: A logic gate array is provided. The logic gate comprises a silicon substrate, a first logic gate layer on top of the silicon substrate, a second logic gate layer on top of the first logic gate layer, and a routing layer between the first and second logic gate layers for routing magnetic gates in the first and second logic gate layers, wherein the first logic gate layer, the second logic gate layer, and the routing layer are electrically connected by vias.

Abstract: An apparatus to store electrical energy is provided. The apparatus includes a first magnetic section, a second magnetic section, and a semiconductor section configured between the first magnetic section and the second magnetic section, wherein the junction between the semiconductor section and the first and second magnetic section forms a diode barrier preventing current flow to store electrical energy.

Abstract: A magnetic memory cell is provided. The memory cell includes a metal device, a first word line, and a second word line. The metal device includes a first magnetic layer having a first dipole; a second magnetic layer having a second dipole; and an conductive layer located between the first and second magnetic layers. The first word line is positioned near the first magnetic layer to change the direction of the first dipole. The second word line is positioned near the second magnetic layer to change the direction of the second dipole. A method of reading/writing a bit in the magnetic memory cell is also provided.

Abstract: A magnetic transistor includes a magnetic section, a thin semiconductor layer, a first metal terminal, a second metal terminal, and a third metal terminal. The thin semiconductor layer is disposed on the magnetic section. The first metal terminal is disposed on one end of the magnetic section, acting as a gate of the magnetic transistor and capable of providing a conductive channel in the thin semiconductor layer. The second metal terminal and the third metal terminal are disposed respectively on one end and the other end of the thin semiconductor layer, capable of creating a conductive region. While the magnetic transistor is turned on, a current path is formed between the second metal terminal and the third metal terminal via the thin semiconductor layer.

Abstract: A magnetic random access memory having an extended address transition detection circuit having a chip enable input, a chip write enable input, a data bus connection, and an address bus connection. The extended address transition detection circuit has an extended transition detection signal output. The magnetic random access memory has a timing controller with a timing control input connected to the address transition detection signal output. The chip enable input, the chip write enable input, the data bus connection, and the address bus connection are buffered and driven off chip.

Abstract: Capacitors including a first conductive material having a first upper finger located on an upper plane and a first lower finger located on a lower plane. The capacitor also includes a second conductive material having a second upper finger and a second lower finger, the second upper finger located on the upper plane such that the second upper finger is next to the first upper finger forming a first interface and on top of the first lower finger forming a second interface, the second lower finger located on the lower plane such that the second lower finger is next to the first lower finger forming a third interface and below the first upper finger forming a fourth interface. Finally, the capacitor includes a dielectric material located in the first interface, the second interface, the third interface, and the fourth interface.

Abstract: A word line driver and decoder for use in a magnetic memory includes a main word line driver and a sub word line driver that cooperate to drive current on a selected one from a number of the magnetic memory's word lines. The main word line driver and sub word line driver employ pull up and pull down transistors that configured to drive current on the selected word line in either a read or write ‘0’ direction or a read or write ‘1’ direction in response to control signals that allow reliable magnetic memory operation. An address decoder selects and activates a multiplexer in the sub word line driver to coordinate the current drive. The main word line driver employs current mirrors, transistor switches, and logic control to prevent direct Vdd to Vss shorting in transitioning from ‘0’ and ‘1’, and read and write data storage operations.

Abstract: A magnetic AND/NOR circuit has a first, a second, a third, and a fourth magnetic transistor. These four magnetic transistors as ordinary transistors that can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transistors. The ‘AND’ and ‘NOR’ logic functions of the binary system can be implemented by the control of these metal devices.

Abstract: The method for reducing word line currents in magnetoresistive random access memory (MRAM) includes disposing the MRAM bit between a pair of word lines according to a magnetic field strength is increased when a distance between a magnetic section and its corresponding word line is decreased.

Abstract: An integrated circuit with magnetic memory has a silicon transistor layer, at least one magnetic memory layer, and a metal routing layer. The silicon transistor layer is arranged to generate several logic operation functions. The magnetic memory layer is arranged to store the data required by the logic operation functions. The metal routing layer has several conducting lines to transmit the data between the silicon transistor layer and the magnetic memory layer.

Abstract: A magnetic transistor circuit with the OR, NOR, NAND and AND functions has a first, a second, a third, a fourth magnetic transistor, and a routing line. These four magnetic transistors as ordinary transistors that can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transistors. The OR, NOR, NAND and AND logic functions of the binary system can be implemented by the control of these metal devices.

Abstract: An apparatus to store electrical energy has a first magnetic section, a second magnetic section and a dielectric section configured between the first magnetic section and the second magnetic section. The dielectric section is arranged to store electrical energy, and dipoles of the first magnetic section and the second magnetic section are arranged to prevent electrical energy leakage.