Abstract: A method switches master/slave timing in a communication network without traffic disruption. The method includes a master device informing a slave of timing loss. The master device additionally begins transmitting with timing from a local reference clock and begins receive timing recovery. The slave freezes its receive timing recovery and locks its transmit clock. The master device transitions its transmit timing to use the recovered receive clock. The slave gradually switches to transmitting using its local clock signal. The method may be used in synchronous Ethernet networks.

Abstract: A system and method for squelching a recovered clock in an Ethernet network. In one embodiment the invention provides a method for squelching a recovered clock in an Ethernet network comprising a local node coupled to a remote node by a link, the method including receiving a descrambler status signal, receiving a remote receiver status signal, receiving a link status signal, and squelching the recovered clock signal based on the descrambler status signal, the remote receiver status signal, and the link status signal.

Abstract: A system and method for providing an early indication of link failure in an Ethernet network. In some embodiments an Ethernet PHY determines a link failure if the PHY loses descrambler synchronization, if remote receiver status is determined to indicate a remote receiver failure, or if link status indicates a link failure.

Abstract: A resampler, method of resampling a signal and a bit pump and transceiver employing the same. In one embodiment, the resampler includes an interpolation stage, coupled to an input of the resampler, that receives a one-bit input signal representing at least a portion of a receive signal propagating along a receive path of the bit pump and generates a plurality of intermediate samples from at least two input samples associated with the one-bit input signal. The resampler also includes a selection stage, coupled to the interpolation stage, that receives the plurality of intermediate samples via one delay line of single bits and select one thereof, thereby providing an output sample that corresponds to a phase of the oscillator.

Abstract: A resampler, method of resampling a signal and a bit pump and transceiver employing the same. In one embodiment, the resampler includes an interpolation stage, coupled to an input of the resampler, that receives a one-bit input signal representing at least a portion of a receive signal propagating along a receive path of the bit pump and generates a plurality of intermediate samples from at least two input samples associated with the one-bit input signal. The resampler also includes a selection stage, coupled to the interpolation stage, that selects one of the plurality of intermediate samples thereby providing an output sample that corresponds to a phase of an oscillator associated with the bit pump.

Abstract: An interpolator, method of interpolating a one-bit signal and resampler employing the interpolator and method. The interpolator employs a cascaded architecture to interpolate a one-bit input signal received at an input thereof. In one embodiment, the interpolator includes a multiple order interpolation filter that generates a sample range from at least three input samples associated with the one-bit input signal. The interpolator further includes a linear interpolation filter, associated with the multiple order interpolation filter, that develops a plurality of samples within the sample range.

Abstract: An audio information processing subsystem 200 is disclosed which includes a stream processor 100 for simultaneously processing multiple streams of audio data. Processing subsystem 200 also includes a program memory 202 coupled to stream processor 100 for storing instructions for controlling processing system 200 and a data memory 203/204 also coupled to stream processor 100. Additionally, a direct memory access circuitry 208 is provided for controlling direct memory accesses to a selected one of program memory 202 and data memory 203/204.