Abstract: An architecture and method for booting a multi-processor system having processor local memory and shared global memory, with shared global memory access managed by an atomic memory access controller and cache coherence managed by software. Reset circuits are used to synchronize to a master clock a commonly distributed start signal and processor individualized restart sequences, which reset circuit signals are distributed to reset both local and global memory. Global memory testing is assigned to a processor based upon its rate status in completing an internal test sequence. The systems and methods are particularly suited to booting a group of multiple but relatively independent processors. Furthermore, the practice of the invention facilitates booting of such system when one or more of the processors have been disconnected or failed.

Abstract: A system and method for managing spare bit steering information in a multi-processor system having a global/local memory architecture. During the system boot cycle one of the multiple processors is selected to test global memory and to configure the steering of the spare bits by bank or the like. Each processor tests its own local memory and defines the associated spare bit steering for the local memory. The global memory spare bit steering configuration information, as well as other global memory configuration information, in the selected processor is distributed to the other processors using registers in a commonly accessible atomic semaphore controller or through a commonly accessible block of global memory. Preferably, the selection of the processor to test the global memory is performed so that no single processor always has the responsibility. In this way, the acquisition of global memory spare bit steering information is not linked to the operative status of any one processor.

Abstract: A method and apparatus are disclosed for monitoring software applications within a first processor during development thereof. A limited number of uniquely identifiable elements or "hooks" are inserted into the software application under development and each time an element is encountered during processing of that software application, the identity of the element and a selected data frame are coupled to the output bus of the first processor. A data output card is utilized to couple that information to a data collection card via a dedicated cable. The data collection card is then utilized to transfer the identity of each element encountered and its associated data frame along with a time value, to a second processor, which is utilized to record that data. In one embodiment of the present invention, a switched bank memory system is utilized in the second processor to permit high speed data storage.