Abstract: This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor.

Abstract: This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor.

Abstract: This disclosure is directed to techniques for preventing or reducing perturbations of an output signal of a differential amplifier caused by ionizing radiation incident upon the amplifier. The amplifier may include an amplification module that includes a plurality of amplification units configured to amplify a difference between a first component and a second component of a differential voltage signal to generate a plurality of amplified difference signals each corresponding to the amplified difference. The amplifier may further include a combination module that combines the plurality of amplified difference signals to generate a common output signal corresponding to the amplified difference.

Abstract: This disclosure is directed to techniques for preventing or reducing perturbations of an output signal of a differential amplifier caused by ionizing radiation incident upon the amplifier. The amplifier may include an amplification module that includes a plurality of amplification units configured to amplify a difference between a first component and a second component of a differential voltage signal to generate a plurality of amplified difference signals each corresponding to the amplified difference. The amplifier may further include a combination module that combines the plurality of amplified difference signals to generate a common output signal corresponding to the amplified difference.

Abstract: A radiation-hardened charge pump circuit is provided. The circuit includes a first charge pump having a first charge pump output, a second charge pump having a second charge pump output, a first coincidence detector receiving as inputs the first charge pump output and the second charge pump output and producing as an output a first coincidence signal, and an analog 2:1 multiplexor for selecting either the first charge pump output or the second charge pump output based on the first coincidence signal. In alternative embodiment, the circuit includes at least three charge pumps, at least two coincidence detectors, decision logic, and a correspondingly-sized analog multiplexor.

Abstract: An integrated circuit has a buried insulation layer formed over a semiconductor substrate, and a semiconductor mesa formed over the buried insulation layer. A low resistivity guard ring substantially surrounds the semiconductor mesa and is in contact with the semiconductor substrate. The low resistivity guard ring is grounded and isolates the semiconductor mesa from RF signals.

Abstract: In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.

Abstract: An integrated circuit has a buried insulation layer formed over a semiconductor substrate, and a semiconductor mesa formed over the buried insulation layer. A low resistivity guard ring substantially surrounds the semiconductor mesa and is in contact with the semiconductor substrate. The low resistivity guard ring is grounded and isolates the semiconductor mesa from RF signals.

Abstract: An integrated circuit has a buried insulation layer formed over a semiconductor substrate, and a semiconductor mesa formed over the buried insulation layer. A low resistivity guard ring substantially surrounds the semiconductor mesa and is in contact with the semiconductor substrate. The low resistivity guard ring is grounded and isolates the semiconductor mesa from RF signals.

Abstract: In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.

Abstract: In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.

Abstract: A radiation-hardened charge pump circuit is provided. The circuit includes a first charge pump having a first charge pump output, a second charge pump having a second charge pump output, a first coincidence detector receiving as inputs the first charge pump output and the second charge pump output and producing as an output a first coincidence signal, and an analog 2:1 multiplexor for selecting either the first charge pump output or the second charge pump output based on the first coincidence signal. In alternative embodiment, the circuit includes at least three charge pumps, at least two coincidence detectors, decision logic, and a correspondingly-sized analog multiplexor.

Abstract: A radiation sensor and a method for making the radiation sensor are described. An ionizing radiation sensitive area is formed in a radiation insensitive or hardened die. When the sensitive area is impacted by ionizing radiation, properties of the sensitive area change. For example, the changed property may be charge density, threshold voltage, leakage current, and/or resistance. Circuitry for measuring these property changes is located in a radiation hardened area of the die. As a result, a radiation sensor may be fabricated on a single die.

Abstract: A differential charge pump with common mode and active regulators is presented. Either type of regulator may be used to improve the performance characteristics of the differential charge pump. The active regulator increases the output range of the differential amplifier. The common mode regulator establishes the common mode voltage of the differential charge pump. The common mode voltage is established independently from external circuitry and does not use a feedback path. The common mode regulator may also be used to establish a mid-rail voltage, which may be used to further improve the output range of the differential amplifier.

Abstract: A radiation sensor and a method for making the radiation sensor are described. An ionizing radiation sensitive area is formed in a radiation insensitive or hardened die. When the sensitive area is impacted by ionizing radiation, properties of the sensitive area change. For example, the changed property may be charge density, threshold voltage, leakage current, and/or resistance. Circuitry for measuring these property changes is located in a radiation hardened area of the die. As a result, a radiation sensor may be fabricated on a single die.

Abstract: A system and method for generating a reset signal within a Phase Locked Loop (PLL) circuit is described. The reset signal is generated by inputting a reference signal and a lock detect signal into reset circuitry. The reset circuitry within the PLL comprises a series of interconnected latches, or D flip-flops, which are used to create a delay time. The delay time is the amount of time the reset circuit will wait until the reset signal indicates a reset. The reset circuit may also generate a reset signal having a pulse width. The pulse width is determined by the series of interconnected latches. The reset signal may be used to reset a Voltage Controlled Oscillator (VCO) or other circuits within a PLL or it may be used by circuits external to the PLL.

Abstract: An apparatus and method for providing a stable gain over wide frequency range in a VCO are presented. A VCO uses a waveform generator along with a bias generator having a frequency select input. The frequency select input is used to adjust the amount of output current and/or gain of the bias generator. The output current of the bias generator determines the frequency of the output of the waveform generator. Multiple bias and waveform generators may be used to expand the frequency range of the VCO. A PLL may be programmed for a variety of output frequencies by using the frequency select input of the VCO.

Abstract: An improved system and method for determining the lock condition of a Phase Locked Loop (PLL) is described. The lock detect circuit generates a fast lock detect signal that may be used to detect a transient loss of lock. The lock detect circuit may also include a phase alignment detect circuit to detect a misalignment in the phase of a reference clock and a feedback clock. Additionally, the lock detect circuit may include a reference clock detect circuit to detect if the reference clock signal is detected. Output signals from all of the above circuits may be communicated to a logic circuit in order to create an enhanced lock detect signal. An extended lock detect signal may also be communicated to the logic circuit.

Abstract: An apparatus and method for providing a power supply compensated voltage or current is presented. A supply compensated current and voltage source utilizes a differential amplifier connected to a bandgap reference voltage and a scaled power supply voltage. When power supply varies, the differential amplifier regulates a stable compensated output. The output may be a compensated voltage or current. In addition, multiple currents and voltages may be referenced from the differential amplifier. The stable compensated output may be supplied as a reference bias for external circuitry. In addition, the compensated output may be supplied to a voltage controlled oscillator.

Abstract: An integrated circuit capacitor includes a silicon-on-insulator (SOI) substrate and a doped epitaxial layer of a first conductivity type formed on the SOI substrate. The doped epitaxial layer is used as a first plate of the integrated circuit capacitor. A gate oxide layer is formed on the doped epitaxial layer and is used as a dielectric layer of the integrated circuit capacitor. A polysilicon gate is formed on the gate oxide layer and is used as a second plate of the integrated circuit capacitor.