Abstract: A dual ported (simultaneous read/write) SRAM block with an additional load port that interacts with the circuitry employed in the loading and testing of the configuration data of the FPGA core is disclosed. Each SRAM block contains circuits in both the read port and the write port that permit the SRAM blocks to be connected into deeper and wider configurations by without any additional logic as required by the prior art. An address collision detector is provided such that when both read and write ports in the SRAM block access the same address simultaneously a choice between the data being read can be made between the data presently in the SRAM block or the new data being written to the SRAM block.

Abstract: The method and apparatus of the current invention relates to an intelligent cache management system for servicing a main memory and a cache. The cache resources are allocated to segments of main memory rows based on a simple or complex allocation process. The complex allocation performs a predictive function allocating scarce resources based on the probability of future use. The apparatus comprises a main memory coupled by a steering unit to a cache. The steering unit controls where in cache a given main memory row segment will be placed. The operation of the steering unit is controlled by an intelligent cache allocation unit. The unit allocates new memory access requests cache locations which are least frequently utilized. Since a given row segment may be placed anywhere in a cache row, the allocation unit performs the additional function of adjusting the column portion of a memory access request to compensate for the placement of the requested segment in the cache.

Abstract: A computer system with a hybrid main memory which includes both EDRAM and DRAM, with a DRAM cache provided within a designated portion of the EDRAM portion of the main memory. Read requests are handled by copying data being read from DRAM into a cache portion of EDRAM under the direction of a pseudo cache controller and decoder which converts the DRAM address to a EDRAM address corresponding to the cache location of EDRAM. Read "hit" requests are responded to by reading data directly from the cache portion of EDRAM. Write requests to DRAM are, for purposes of cache coherency when a copy of the address being written to is present in the EDRAM cache portion, accomplished by writing data both to DRAM and overwriting the stale data existing in the cache portion of EDRAM.

Abstract: An EDRAM device includes an EDRAM memory array on a semiconductor chip. A row enable signal generator and a column address latch signal generator are provided on the same semiconductor chip for generating row enable and column address latch signals for application to the EDRAM memory array.

Abstract: A method and apparatus for use in computer systems utilizes a memory chip employing multiple distributed SRAM caches directly linked to a single DRAM main memory block. Each cache is directly linked to a different bus. Each chip further contains a partially distributed arbitration and control circuit for implementing cache policy and arbitrating memory refresh cycles.