Abstract: A system and method are described for providing automated incremental compilation of computer programs. The system has a library generation logic that generates a dynamic link library of a plurality of computer programs, and a work area creation logic that creates a program work area. A program copy logic copies at least one computer program into the program work area to enable the computer program to be modified. A program generation logic then generates an executable program that includes all of the computer programs in said program work area and the plurality of computer programs in the dynamic link library.

Abstract: The system is a method and an apparatus for resteering failing speculation check instructions in the pipeline of a processor. A branch offset immediate value and an instruction pointer correspond to each failing instruction. These values are used to determine the correct target recovery address. A relative adder adds the immediate value and the instruction pointer value to arrive at the target recovery address. This is done by flushing the pipeline upon the occurrence of a failing speculation check instruction. The pipeline flush is extended to allow the instruction stream to be resteered. The immediate value and the instruction pointer are then routed through the existing data paths of the pipeline, into the relative adder, which calculates the correct address. A sequencer tracks the progression of these values through the pipeline and causes a branch at the desired time.

Abstract: A method and apparatus for handling errors that deadlock a CPU by first attempting to resolve the deadlock without issuing a bus error and without restarting the CPU. If the deadlock cannot be resolved without issuing a bus error, then a bus error is issued and the CPU attempts to restart. The method involves comparing the number of clock cycles taken to execute an instruction to a designated abort value. When an instruction has taken the full abort value of cycles but has not retired, a machine-check abort (MCA) is issued to attempt to resolve the deadlock. The method also involves comparing the number of clock cycles to a larger bus error value. If the MCA does not break the deadlock within a certain period—i.e., before the bus error value is reached—then a bus error is issued and the machine attempts to reset.