Abstract: A process for improving the grade and optical quality of zircon, comprising: baking a mixture of a zircon feed and concentrated sulphuric acid at a baking temperature in the range of from 200 up to 400° C., and for a time to form water leachable sulphates with impurities therein including at least iron and titanium; leaching the baked mixture to dissolve the leachable sulphates; and separating the zircon from the leachate containing the leached sulphates, which separated zircon is thereby of improved grade and optical quality.

Abstract: A process for improving the grade and optical quality of zircon, comprising: baking a mixture of a zircon feed and concentrated sulphuric acid at a baking temperature in the range of from 200 up to 400° C., and for a time to form water leachable sulphates with impurities therein including at least iron and titanium; leaching the baked mixture to dissolve the leachable sulphates; and separating the zircon from the leachate containing the leached sulphates, which separated zircon is thereby of improved grade and optical quality.

Abstract: A method and apparatus to utilize a fetching scheme for instructions in a processor to limit the expenditure of power caused by the speculative execution of branch instructions is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes calculating a cumulative confidence measure based on one or more outstanding conditional branch instructions. The method also includes reducing prefetching operations in response to detecting that the cumulative confidence measure is below a first threshold level.

Abstract: A method and apparatus for eliminating fetch cancels for inclusive caches are presented. Some embodiments of the apparatus include a first cache configurable to issue fetch or prefetch requests to a second cache that is inclusive of said at least one first cache. The first cache is not permitted to cancel issued fetch or prefetch requests to the second cache. Some embodiments of the method include preventing the first cache(s) from canceling issued fetch or prefetch requests to a second cache that is inclusive of the first cache(s).

Abstract: A method and apparatus for eliminating fetch cancels for inclusive caches are presented. Some embodiments of the apparatus include a first cache configurable to issue fetch or prefetch requests to a second cache that is inclusive of said at least one first cache. The first cache is not permitted to cancel issued fetch or prefetch requests to the second cache. Some embodiments of the method include preventing the first cache(s) from canceling issued fetch or prefetch requests to a second cache that is inclusive of the first cache(s).

Abstract: A method and apparatus to utilize a fetching scheme for instructions in a processor to limit the expenditure of power caused by the speculative execution of branch instructions is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes calculating a cumulative confidence measure based on one or more outstanding conditional branch instructions. The method also includes reducing prefetching operations in response to detecting that the cumulative confidence measure is below a first threshold level.

Abstract: A method and apparatus for dual-target register allocation is described, intended to enable the efficient mapping/renaming of registers associated with instructions within a pipelined microprocessor architecture.

Abstract: A method and apparatus for dual-target register allocation is described, intended to enable the efficient mapping/renaming of registers associated with instructions within a pipelined microprocessor architecture.

Abstract: A method and apparatus for dual-target register allocation is described, intended to enable the efficient mapping/renaming of registers associated with instructions within a pipelined microprocessor architecture.