Abstract: An apparatus for use in an addressable distributed wireless remote control system includes a receiver operative to receive a request from an unidentified remote control device via a wireless communication medium. The apparatus also includes a storage device to store an identifier which identifies the receiver in the system, and transmit logic, coupled to the receiver and the storage medium, operative to transmit both the request and the identifier to a system controller.

Abstract: An apparatus for use in an addressable distributed wireless remote control system includes a receiver operative to receive a request from an unidentified remote control device via a wireless communication medium. The apparatus also includes a storage device to store an identifier which identifies the receiver in the system, and transmit logic, coupled to the receiver and the storage medium, operative to transmit both the request and the identifier to a system controller.

Abstract: An apparatus for use in a member hardware system of a distributed collection of hardware systems includes monitor logic that cooperates with like logic of the other hardware systems to collectively monitor wellness of all hardware systems of the distributed collection of hardware systems and determine whether the hardware systems should be re-synchronized. The apparatus also includes reset logic communicatively coupled with the monitor logic that resets the member hardware system and causes the member hardware system to be rebooted off a common system image disposed in a boot one of the distributed collection of hardware systems, responsive to the monitor logic determining the hardware systems should be re-synchronized.

Abstract: Each member system of a distributed collection of self-monitoring hardware systems includes receiving logic operative to receive a wellness token from a first other hardware system of the distributed collection of hardware systems. Each member system also includes modification logic, communicatively coupled to the receiving logic, operative to modify the wellness token to create a modified wellness token in a manner that reflects the wellness of the member hardware system, and transmitting logic, communicatively coupled to the modification logic, operative to transmit the modified wellness token to a second other hardware system of the distributed collection of hardware systems.

Abstract: A computer system providing a universal architecture includes a processor card connected to a system bus of a host computer system. The processor card is adapted for insertion into a slot of the computer system and houses a processor and a bus bridge conversion device. The processor operates according to a signaling protocol which is different than the signaling protocol of the computer system bus. The bus conversion device converts the signaling protocol of the system bus to the signaling protocol of the processor, and vice-versa. The bus conversion device includes logic for bus arbitration conversion, bus lock conversion, and cache coherency control. Logic is also included that converts incoming and outgoing requests so that the card may properly transact with other agents coupled to the bus.

Abstract: A method of operation in a computer system having a host processor, a pipelined system bus, and at least one agent, all of which operate in accordance with a first signaling protocol, and a processor that is included in a subsystem that operates according to a second signaling protocol which is incompatible with the first signaling protocol. The method comprises the steps of converting arbiter signals generated by the subsystem processor from the second signaling protocol to the first signaling protocol of the pipelined bus to obtain ownership of the pipelined bus. Next, an outgoing request encoding of the processor is translated from the second signaling protocol to the first signaling protocol. Finally, generating a bus cycle on the pipelined bus from the translated outgoing request encoding in accordance with the first signaling protocol of the pipelined bus.

Abstract: A processor subsystem includes a processor and a bus bridge conversion device for insertion into a slot of a host computer system. The processor operates according to a signaling protocol which is different than the signaling protocol of the computer system bus. The bus conversion device converts the signaling protocol of the system bus to the signaling protocol of the processor, and vice-versa. The bus conversion device includes logic for bus arbitration conversion, bus lock conversion, and cache coherency control. Logic is also included that converts incoming and outgoing requests so that the card may properly transact with other agents coupled to the bus.

Abstract: A dual deadman timer circuit functions to reset a dual mode microprocessor in the event of loss of program control. The microprocessor has high and low power requirements corresponding to its two operating modes, and the deadman timer circuit also adjusts the output power level of an associated two-level power supply to ensure that sufficient power is available for the full operation of the microprocessor during reset. The deadman timer functions during both microprocessor modes and includes two level-sensitive input sections to ensure that the microprocessor is reset under an error condition.

Abstract: A DC/DC converter operates at peak efficiency in either of two output current level states in response to the power demands of an associated electronic device, thereby reducing wasted current to a minimum. The converter is designed to operate from a one-cell battery, and is particularly suited to an integrated circuit implementation.