Abstract: A multiplier includes an input stage to receive input signals to provide currents at a plurality of source nodes. An output stage includes a plurality of transistor groups, each of the transistor groups includes a plurality of transistor pairs. The values of currents produced by the output stage can be controlled by selecting appropriate parameters of the transistor pairs.

Abstract: A current summing FIR filter can be implemented with multiple differential input stages and variable tail currents. The variable tail currents can be used to appropriately weight the present and previous digital input signals. The weighted outputs of the differential transistor pairs can be summed to provide a filtered output signal. The tail currents can be advantageously varied with variable current sources or by adjustment of the relative widths of the differential transistor pairs. In other embodiments, additional differential pairs can be added to adjust for systematic offset voltages caused by process-induced variations in the structure of circuit devices or to induce a desired offset.

Abstract: An amplifier includes multiple stages. Early stages of the multi-stage amplifier have low gain and preserve bandwidth.

Abstract: A digital interconnect system transmits pulses across a differential transmission line in response to transitions in an input data signal.

Abstract: An optical receiver includes a photodiode, a variable current source, and a current mode comparator to detect a difference between current from the photodiode and current from the variable current source.

Abstract: An amplifier includes a differential unit including an input port to receive a voltage input signal, a current mirror unit including an output port, and a voltage-to-current conversion unit to couple the differential unit to the current mirror unit and to generate a current signal to drive the current mirror unit to generate a current output signal at the output port. A method includes receiving a voltage input signal at an input port of a differential unit, converting the voltage input signal to a current signal, and driving a current mirror with the current signal to generate an current output signal at an output port.

Abstract: A memory system provides includes multiple memory devices or banks of memory devices that are assigned frequency pass-bands. Each memory device includes frequency translation circuitry to up-convert and down-convert data signals to and from the assigned frequency pass-band. Some embodiments include simultaneous bidirectional communications between memory devices and a controller by assigning multiple frequency pass-bands to each memory device or bank of memory devices. A memory system substrate is provided with bandpass filters between memory device footprints and other device footprints.

Abstract: An amplifier includes multiple gain ranges. The gain range can be set by electrically adding or removing load devices.

Abstract: A port circuit includes circuitry to capture a waveform. The port circuit may be a unidirectional port circuit, or a bidirectional port circuit.

Abstract: A comparator unit includes a first amplifier stage and a second amplifier stage. The first amplifier stage includes a differential amplifier having a pair of input nodes for receiving a differential signal and a pair of output nodes, a switch connected across the pair of output nodes, and a non-linear load connected across the pair of output nodes. The second amplifier stage is coupled to the pair of output nodes of the first amplifier stage. In one embodiment the second amplifier stage is a non-linear amplifier. In an alternative embodiment, the differential amplifier is a differential pair. In another alternative embodiment, the differential amplifier is a pair of differential pairs.

Abstract: An amplifier includes a differential pair including a pair of input ports and a pair of output ports and a nonlinear load coupled to the differential pair. The pair of output ports is coupled to the pair of input ports to provide negative feedback. The pair of output ports is coupled to the non-linear load to provide positive feedback. A method includes receiving a signal at an input port of an amplifier and processing the signal in the amplifier by coupling negative feedback and positive feedback produced in the amplifier by the signal to the input port.

Abstract: An amplifier includes multiple gain ranges. The gain range can be set by electrically adding or removing load devices.

Abstract: An amplifier includes multiple stages. Early stages of the multi-stage amplifier have low gain and preserve bandwidth.

Abstract: A current summing FIR filter can be implemented with multiple differential input stages and variable tail currents. The variable tail currents can be used to appropriately weight the present and previous digital input signals. The weighted outputs of the differential transistor pairs can be summed to provide a filtered output signal. The tail currents can be advantageously varied with variable current sources or by adjustment of the relative widths of the differential transistor pairs. In other embodiments, additional differential pairs can be added to adjust for systematic offset voltages caused by process-induced variations in the structure of circuit devices or to induce a desired offset.

Abstract: First and second differential transistor pairs, where each may be intentionally unbalanced or balanced, are provided. First and second digitally variable current generators are coupled to control respective tail currents of the first and second differential pairs. A switch circuit may be coupled to equalize the voltages of the respective tail current nodes. A common mode feedback circuit is also described, to improve common mode rejection of the overall amplifier. Applications of the amplifier circuit include sense amplifiers and comparators.

Abstract: An active cascode differential latch for providing a logic output signal indicative of whether or not a first current is greater than a second current. The first and second currents are fed into two input ports of the active cascode differential latch. The active cascode differential latch has a relatively small input impedance, and has utility for comparators and discrete-time analog filters, to name just a few, particularly when used in high bandwidth and low voltage applications.

Abstract: A discrete-time analog filter, where a filter tap of the filter comprises a voltage-to-current converter, an active current mirror, and a current multiplier to provide a current signal indicative of a weighted sampled voltage signal. The current signals from the filter taps are summed by one or more active cascode differential latches to provide an output logic signal indicative of the filtered output. The discrete-time analog filter finds applications in channel equalization, and is suitable for high data rates and low voltage applications. The voltage and current signals may be differential. The voltage-to-current converter may include a common-mode high-pass filter to reject common-mode voltage variations.

Abstract: A CMOS amplifier for optoelectronic receivers, the amplifier comprises two transimpedance amplifiers and two differential amplifier latches. One of the two transimpedance amplifiers has an input port to receive a current signal, such as, for example, a current signal from a photodetector, and provides a output voltage indicative of the received current signal. The other of the two transimpedance amplifiers may be viewed as having no input signal, so that it provides a reference voltage. The two transimpedance amplifiers are in close proximity to each other, so that power supply noise is a common mode signal in the output voltages of the two transimpedance amplifiers. The differential amplifier latches reject the common mode signal by comparing the reference voltage to the output voltage, and provide output logic voltages indicative of binary hard decisions.

Abstract: According to some embodiments, a device includes a phase generator to generate m control signals, each of the m control signals associated with a respective signal period, and at least m filters, each of the at least m filters comprising m-n taps, each of the m-n taps to receive one of the m control signals, to acquire a signal sample according to a signal period associated with the received control signal, and to modulate the signal sample according to a weighting coefficient associated with the tap. The device further includes m evaluation circuits, each evaluation circuit associated with a respective one of the at least m filters and to output a sum of signal samples modulated by the taps of the associated filter in response to one of the m control signals associated with a signal period other than the signal periods according to which the signal samples were acquired.

Abstract: An information transmission unit includes a signal source, a channel having a channel cutoff frequency coupled to the signal source, a continuous-time linear active filter coupled to the channel to provide equalization over a range of frequencies, and a sampling unit coupled to the continuous-time linear active filter. A method includes transmitting a continuous time signal including digital information on a channel, receiving the continuous time signal from the channel and filtering the continuous time signal to form an equalized continuous time signal, and sampling the equalized continuous time signal to recover the digital information.