Abstract: A system and method for power management in a computer system having multiple power grids is disclosed. The system includes a service structure operable in conjunction with an operating system (OS) instance executed on the computer system. At least one uninterrupted power supply (UPS) and at least one alternative source of power provide power to the multiple power grids. Where an UPS sends a loss of power notification to the service structure, the service structure is operable to maintain power supply to the grids from an available alternative source of power.

Abstract: A system and method for power management in a computer system having multiple power grids is disclosed. The system includes a service structure operable in conjunction with an operating system (OS) instance executed on the computer system. At least one uninterrupted power supply (UPS) and at least one alternative source of power provide power to the multiple power grids. Where an UPS sends a loss of power notification to the service structure, the service structure is operable to maintain power supply to the grids from an available alternative source of power.

Abstract: A computer system having a plurality of independent processors which can either execute a separate process for each processor, or execute parallel process operations across multiple processors for one process. The computer system includes a set of communication registers divided into a group of frames and a set of semaphores which correspond respectively to the registers. Typical processes have both serial and parallel code segments. During serial execution, a process is executed by a single processor, but when a parallelization instruction is encountered, which indicates that code can be executed in parallel, a semaphore is posted to invite other processors to join in parallel execution of the process. If any other processors in the system are idle, those processors detect the semaphore and accept a thread of process operation. Two or more processors may join in parallel operation if sufficient operations are available.

Abstract: A computer system comprises a plurality of independent processors which can either execute a separate process for each processor, or execute parallel process operations across multiple processors for one process. The computer system includes a set of communication registers divided into a group of frames and a set of semaphores which correspond respectively to the registers. Typical processes have both serial and parallel code segments. During serial execution, a process is executed by a single processor, but when a parallelization instruction is encountered, which indicates that code can be executed in parallel, a semaphore is posted to invite other processors to join in parallel execution of the process. If any other processors in the system are idle, those processors detect the semaphore and accept a thread of process operation. Two or more processors may join in parallel operation if sufficient operations are available.

Abstract: A vector processing computer is configured to operate in a pipelined fashion wherein each of the functional units is essentially independent and is designed to carry out its operational function in the fastest possible manner. Vector elements are transmitted from memory, either main memory, a physical cache unit or a logical cache through a source bus where the elements are alternately loaded into the vector processing units. The vector control unit decodes the vector instructions and generates the required control commands for operating the registers and logical units within the vector processing units. Thus, the vector processing units essentially work in parallel to double the processing rate. The resulting vectors are transmitted through a destination bus to either the physical cache unit, the main memory, the logical cache or to an input/output processor.