Patents by Inventor James E. Margeson, III
James E. Margeson, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6961057Abstract: A computer graphics system provides for processing image data including Z data for use in displaying three-dimensional images on a display unit. The system includes: a depth buffer providing for temporary storage of Z data; and a graphics processing unit having a graphics engine for generating image data including Z data, and a memory interface unit communicatively coupled to the graphics engine and communicatively coupled to the depth buffer via a depth buffer interface. The graphics processing unit is operative to compress at least a portion of the generated Z data, to write the compressed portion of Z data to the depth buffer via the depth buffer interface in a compressed format, to read portions of compressed Z data from the depth buffer via the depth buffer interface, and to decompress the compressed Z data read from the buffer.Type: GrantFiled: October 12, 2000Date of Patent: November 1, 2005Assignee: NVIDIA CorporationInventors: James M. Van Dyke, James E. Margeson, III
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Patent number: 6850243Abstract: A system, method and computer program product are provided for texture sampling in a graphics pipeline. Initially, texture information is retrieved using texture coordinates. Thereafter, the texture information is utilized to generate results. Next, the texture information and the results are utilized to generate further results. The foregoing operation may optionally be repeated, and the results outputted.Type: GrantFiled: November 27, 2001Date of Patent: February 1, 2005Assignee: NVIDIA CorporationInventors: Emmett M. Kilgariff, James E. Margeson, III, Dane Thomas Mrazek
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Patent number: 6734861Abstract: A system, method and article of manufacture are afforded for providing an interlock module in a graphics pipeline. initially, first information is received indicative of a first set of pixels that overlap a primitive. Such first set of pixels are currently being processed in the graphics pipeline. Also received is second information indicative of a second set of pixels that overlap the primitive. The second set of pixels are ready for being inputted in the graphics pipeline for processing. Thereafter, the first information and the second information are evaluated, and the second set of pixels is conditionally processed based on the evaluation.Type: GrantFiled: October 16, 2000Date of Patent: May 11, 2004Assignee: nVidia CorporationInventors: James M. Van Dyke, Douglas A. Voorhies, James E. Margeson, III, John Montrym
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Patent number: 5870102Abstract: A texture compositing apparatus and method for combining multiple independent texture colors in a variety of ways in a single execution pass using a single texture compositing unit (TCU) per texture. The TCU receives a control signal, a blend factor, a local data signal(C.sub.local /A.sub.local) and an output data signal (C.sub.in /A.sub.in) generated by another TCU, the local data signal and the output data signal represent a texture color in a RGBA format. Based upon the control signal, the TCU can generate an output signal based on a variety of functions. The outputs that can be generated include but are not limited to: (1) zero; (2) one; (3) C.sub.in ; (4) C.sub.local ; (5) C.sub.in +C.sub.local ; (6) C.sub.in -C.sub.local ; (7) C.sub.in *C.sub.local ; (8) C.sub.in *C.sub.local +A.sub.local ; (9) C.sub.in *A.sub.local +C.sub.local ; (10) (C.sub.in -C.sub.local)* F.sub.blend +C.sub.local ; and (11) (C.sub.in -C.sub.local)*(1-F.sub.blend)+C.sub.local.Type: GrantFiled: April 8, 1998Date of Patent: February 9, 1999Assignee: 3Dfx Interactive, IncorporatedInventors: Gary Tarolli, Scott Sellers, James E. Margeson, III
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Patent number: 5831624Abstract: A high quality texture filtering technique in a computer hardware system. The texture filtering quality of the present invention is comparable to trilinear filtering. However, the present invention reduces the number of memory accesses by fifty percent in comparison to trilinear filtering. To achieve this result, the present invention determines a pixel value based upon one or more texel values, e.g., four texel values, from only one of two mipmap levels. The mipmap level that is used is based upon the fractional portion of the LOD value and the position of the pixel. For a group of pixels having the same LOD value, the present invention performs a dithering operation that results in some pixel values being determined using texel values from the lower level mipmap and the remaining pixel values being determined using texel values from the higher level mipmap.Type: GrantFiled: April 30, 1996Date of Patent: November 3, 1998Inventors: Gary Tarolli, Scott Sellers, James E. Margeson, III
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Patent number: 5822452Abstract: A system and method for compressing and decompressing a texture image that: (1) compresses each texel to 8 bits, and when decompressed, each texel is of a quality comparable to a 256 color palettized image; (2) increases the efficiency of the decompression system and method by eliminating complex operations, e.g., multiplication; and (3) increases the efficiency of the system and method when switching between textures that use different palettes, when compared to conventional system and methods. The invention compresses a texture image, stores the compressed texture image, and quickly and efficiently decompresses the texture image when determining a value of a pixel. The texture image compression technique utilizes a palletized color space that more closely matches the colors in the texture image while allocating an unequal number of bits to the color channels.Type: GrantFiled: April 30, 1996Date of Patent: October 13, 1998Assignee: 3Dfx Interactive, Inc.Inventors: Gary Tarolli, Scott Sellers, James E. Margeson, III, Murali Sundaresan
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Patent number: 5740343Abstract: A texture compositing apparatus and method for combining multiple independent texture colors in a variety of ways in a single execution pass using a single texture compositing unit (TCU) per texture. The TCU receives a control signal, a blend factor, a local data signal(C.sub.local /A.sub.local), and an output data signal (C.sub.in /A.sub.in) generated by another TCU, the local data signal and the output data signal represent a texture color in a RGBA format. Based upon the control signal, the TCU can generate an output signal based on a variety of functions. The outputs that can be generated include but are not limited to: (1) zero; (2) one; (3) C.sub.in ; (4) C.sub.local ; (5) C.sub.in +C.sub.local ; (6) C.sub.in -C.sub.local ; (7) C.sub.in *C.sub.local ; (8) C.sub.in *C.sub.local +A.sub.local ; (9) C.sub.in *A.sub.local +C.sub.local ; (10) (C.sub.in -C.sub.local)*F.sub.blend +C.sub.local ; and (11) (C.sub.in -C.sub.local)*(1-F.sub.blend)+C.sub.local.Type: GrantFiled: November 3, 1995Date of Patent: April 14, 1998Assignee: 3DFX Interactive, IncorporatedInventors: Gary Tarolli, Scott Sellers, James E. Margeson, III
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Patent number: 5473572Abstract: A memory controller is provided in which the address path is disabled by a sequencer to reduce power consumption when the sequencer is in an IDLE mode. When access is requested by the bus, the sequencer changes into an ALERT mode, thereby enabling the address path. Subsequently the sequencer then changes into an EXECUTE mode to perform data transfer operations. After the transfer is completed, the sequencer returns to the ALERT mode and an inactive time counter begins counting. If no access is requested before the counter reaches a predetermined number of counts, the sequencer returns to the IDLE mode and the address path is disabled to save power. However, if another cycle request occurs while in the ALERT mode, the EXECUTE mode is entered into immediately.Type: GrantFiled: October 18, 1994Date of Patent: December 5, 1995Assignee: Chips and Technologies, Inc.Inventor: James E. Margeson, III
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Patent number: 5448257Abstract: A frame buffer architecture for a graphics controller provides for conversion of cathode ray tube (CRT) data streams to multi-segment data streams. The buffer architecture operates such that the CRT frame rate is the same as the multi-segment frame rate. In so doing, a graphics controller can operate within its intended specification while operating at the same clock frequency whether in CRT or multi-segment mode. In addition, this architecture overcomes the other problems associated with prior art graphics controllers.Type: GrantFiled: July 18, 1991Date of Patent: September 5, 1995Assignee: Chips and Technologies, Inc.Inventors: James E. Margeson, III, Ignatius B. Tjandrasuwita
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Patent number: 5422654Abstract: The present invention relates to An apparatus for converting cathode ray tube (CRT) to a dual panel data stream to be utilized. The present invention includes a frame buffer system for displaying data on a dual panel display, which comprises an upper and lower panel. The frame buffer system receives CRT data and displays panel refresh data in which one CRT frame generates one panel refresh frame. Through the use of this system, An increased number of gray level patterns can be provided, thereby increasing image resolution and quality.Type: GrantFiled: March 18, 1994Date of Patent: June 6, 1995Assignee: Chips and Technologies, Inc.Inventors: Ignatius B. Tjandrasuwita, James E. Margeson, III
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Patent number: RE37069Abstract: The present invention relates to An apparatus for converting cathode ray tube (CRT) data to a dual panel data stream to be utilized. The present invention includes a frame buffer system for displaying data on a dual panel display, which comprises an upper and lower panel. The frame buffer system receives CRT data and displays panel refresh data in which one CRT frame generates one panel refresh frame four panel refresh frames. Through the use of this system, An increased number of gray level patterns can be provided, thereby increasing image resolution and quality.Type: GrantFiled: August 29, 1995Date of Patent: February 27, 2001Assignee: Chips & Technologies, LLCInventors: Ignatius B. Tjandrasuwita, James E. Margeson, III