Abstract: A paint overspray particulate filtration system includes a collection tank, a floatation consolidation tank, and a vacuum filter assembly having a filter medium that traverses a pair of vacuum chambers. A positive displacement vacuum producer for the first vacuum chamber discharges a first supply of pressurized air at a temperature preferably greater than about 170° F. and a pressure preferably greater than about 6 psig, while a centrifugal compressor discharges a second supply of pressurized air at a temperature of perhaps up to 110° F. and at a pressure of perhaps 4 psig. The first pressurized air supply is heat exchanged with the second pressurized air supply, whereupon the cooled first pressurized air supply is directed through a submerged diffuser nozzle to aerate the collection tank and/or the consolidation tank. The warmed second pressurized air supply is directed onto the paint sludge carried atop the filter medium to enhance sludge dewatering.

Abstract: A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. This circuit is driven by an additional output vector from the circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.

Abstract: A memory device including a circuit for actively driving a reference voltage in a memory device is disclosed. A circuit integrated in a memory device and coupled to an external voltage source substantially eliminates fluctuations in the reference voltage of the memory device caused by power supply changes and noise occurring in the memory device by generating a constant voltage and good current drive from the external voltage source.

Abstract: As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing.

Abstract: A paint overspray particulate filtration system includes a collection tank, a floatation consolidation tank, and a vacuum filter assembly having a filter medium that traverses a pair of vacuum chambers. A positive displacement vacuum producer for the first vacuum chamber discharges a first supply of pressurized air at a temperature preferably greater than about 170° F. and a pressure preferably greater than about 6 psig, while a centrifugal compressor discharges a second supply of pressurized air at a temperature of perhaps up to 110° F. and at a pressure of perhaps 4 psig. The first pressurized air supply is heat exchanged with the second pressurized air supply, whereupon the cooled first pressurized air supply is directed through a submerged diffuser nozzle to aerate the collection tank and/or the consolidation tank. The warmed second pressurized air supply is directed onto the paint sludge carried atop the filter medium to enhance sludge dewatering.

Abstract: Circuits and methods are provided that reduce, if not prevent, the adverse effects of transient noise on phase adjustments made by digital delay lock loop (DLL) circuits, which typically generate a periodic output signal having a particular phase relationship with a periodic input signal. A digital low pass filter of a DLL circuit includes circuitry, such as, for example, a thermometer register, coupled to receive the outputs of a DLL phase detector. The low pass filter prevents the DLL circuit from making frequent changes to the phase of the DLL output signal.

Abstract: A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. This circuit is driven by an additional output vector from the circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.

Abstract: As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing.

Abstract: A circuit and method for actively driving a reference voltage in a memory device is disclosed. A circuit integrated in a memory device and coupled to an external voltage source substantially eliminates fluctuations in the reference voltage of the memory device caused by power supply changes and noise occurring in the memory device by generating a constant voltage and good current drive from the external voltage source.

Abstract: A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. This circuit is driven by an additional output vector from the circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.

Abstract: Circuits and methods are provided that reduce, if not prevent, the adverse effects of transient noise on phase adjustments made by digital delay lock loop (DLL) circuits, which typically generate a periodic output signal having a particular phase relationship with a periodic input signal. A digital low pass filter of a DLL circuit includes circuitry, such as, for example, a thermometer register, coupled to receive the outputs of a DLL phase detector. The low pass filter prevents the DLL circuit from making frequent changes to the phase of the DLL output signal.

Abstract: As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing.

Abstract: As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing.

Abstract: A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. This circuit is driven by an additional output vector from the circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.

Abstract: As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing.

Abstract: As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing.

Abstract: A device includes a first input pin, a second input pin, a differential signal generator, and a differential receiver. The first input pin is adapted to receive a first signal. The second input pin is adapted to receive a second signal. The differential signal generator is coupled to the first and second input pins and adapted to receive an enable signal. The differential signal generator is adapted to isolate the second input pin and generate an internal signal based on an inversion of the first signal in response to the enable signal being asserted. The differential receiver has a first input terminal and a second input terminal. The differential receiver is adapted to receive the first signal at the first input terminal and one of the second signal and the internal signal at the second input terminal and generate a differential output signal. A method for generating a differential signal is provided. A first input signal is received at a first input pin of a device. An enable signal is received.

Abstract: A circuit and method for actively driving a reference voltage in a memory device is disclosed. A circuit integrated in a memory device and coupled to an external voltage source substantially eliminates fluctuations in the reference voltage of the memory device caused by power supply changes and noise occurring in the memory device by generating a constant voltage and good current drive from the external voltage source.

Abstract: A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. This circuit is driven by an additional output vector from the circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.

Abstract: As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing.