Abstract: A communications system including a clock recovery circuit that extracts a clock signal from incoming digital data, the clock recovery circuit comprising:a voltage controlled oscillator having a control node and having an output producing an output wave having a frequency that varies in response to a voltage applied to the control node; charge pump and loop filter circuitry that controls the rate of change of the voltage on the control node of the voltage controlled oscillator; a start-up circuit that performs frequency detection and, in conjunction with the charge pump and loop filter circuitry, adjusts the voltage on the control node of the voltage controlled oscillator; and a state machine that performs phase detection and adjusts the voltage on the control node of the voltage controlled oscillator.

Abstract: A communications system including a clock recovery circuit that extracts a clock signal from incoming digital data, the clock recovery circuit including a voltage controlled oscillator having a control node and having an output producing an output wave having a frequency that varies in response to a voltage applied to the control node; charge pump and loop filter circuitry that controls the rate of change of the voltage on the control node of the voltage controlled oscillator; a start-up circuit that performs frequency detection and, in conjunction with the charge pump and loop filter circuitry, adjusts the voltage on the control node of the voltage controlled oscillator; and a state machine that performs phase detection and adjusts the voltage on the control node of the voltage controlled oscillator.

Abstract: A programmable non-volatile memory device includes a memory array of addressable memory cells and multiple redundant memory cells for replacing defective memory cells in the memory array. To program the memory device, data is written to one or more of the addressable memory cells in the memory array. In the event that the data is not validly written into the address memory cells, repeated attempts are made to program the same memory cells. The memory device includes a counter for counting the number of times the same memory cells are accessed for programming purposes. When a predetermined number of such programming cycles is achieved, the address memory cells are determined to be defective. A redundancy address matching circuit is enabled at this point to replace the defective memory cells with redundant memory cells that can be validly programmed. The memory device subsequently routes the data to the redundant memory cells instead of the defective memory cells.

Abstract: A programmable non-volatile memory device includes a memory array of addressable memory cells and multiple redundant memory cells for replacing defective memory cells in the memory array. To program the memory device, data is written to one or more of the addressable memory cells in the memory array. In the event that the data is not validly written into the address memory cells, repeated attempts are made to program the same memory cells. The memory device includes a counter for counting the number of times the same memory cells are accessed for programming purposes. When a predetermined number of such programming cycles is achieved, the address memory cells are determined to be defective. A redundancy address matching circuit is enabled at this point to replace the defective memory cells with redundant memory cells that can be validly programmed. The memory device subsequently routes the data to the redundant memory cells instead of the defective memory cells.

Abstract: A programmable non-volatile memory device includes a memory array of addressable memory cells and multiple redundant memory cells for replacing defective memory cells in the memory array. To program the memory device, data is written to one or more of the addressable memory cells in the memory array. In the event that the data is not validly written into the address memory cells, repeated attempts are made to program the same memory cells. The memory device includes a counter for counting the number of times the same memory cells are accessed for programming purposes. When a predetermined number of such programming cycles is achieved, the address memory cells are determined to be defective. A redundancy address matching circuit is enabled at this point to replace the defective memory cells with redundant memory cells that can be validly programmed. The memory device subsequently routes the data to the redundant memory cells instead of the defective memory cells.

Abstract: A complementary MOS buffer and amplifier stage is described herein and is useful for operation in a pump circuit of the type where an integrated circuit substrate is driven above Vcc or below ground potential. This operation serves to minimize parasitic capacitance loading and stabilize MOS device thresholds and consumes very little power. The CMOS buffer and amplifier stage includes first and second complementary input transistors cascaded to drive, respectively, first and second complementary output transistors, and lumped resistance means are connected in series between the first and second complementary input transistors and between the gate electrodes of the first and second complementary output transistors.

Abstract: An integrated circuit such as an SRAM or DRAM fabricated in a package having a number of external pins includes a plurality of inputs and outputs electrically coupled to the external package pins, an internal substrate that is unconnected to any of the external pins, a test mode indicator circuit having an input coupled to an external pin and an output for providing a test mode signal and a switch responsive to the test mode signal for coupling the substrate to a predetermined voltage. The predetermined voltage can either be ground, or a negative voltage introduced on a pin that is normally set to a logic zero during package level testing. The test mode signal can also be used to disable the on-chip charge pump. The test mode indicator circuit can include a super voltage indicator, an electronic key, or latch circuit in order to receive the test mode indication signal on an existing package pin.

Abstract: An integrated cirucuit is provided with a depletion mode filter capacitor, which reduces voltage spiking, while at the same time avoiding latchup problems caused by the capacitor. The depletion mode capacitor has a barrier layer which is doped to an opposite conductivity type as the integrated circuit's substrate, achieved by doping to provide an opposite difference from four valence electrons as the substrate. The barrier is formed as a part of a CMOS process, in a manner which avoids additional process steps. The capacitor is formed with one node connected to ground or substrate, and the other node directly to a power bus. The capacitor is located on open space available on the whole siliocn chip (memory as well as logic chip), particularly directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor wth capacitance in excess of 0.001 .mu.F.

Abstract: A test circuit (10) for a semiconductor memory is provided. The semiconductor memory includes a redundant decoder (70) for receiving memory address signals (66, 68) which is connected to a redundant circuit element via a signal line (72). The redundant decoder (70) can be programmed in accordance with the address of a defective circuit element, such that when the decoder (70) is addressed by the memory address signals (66, 68) the decoder (70) selects a predetermined redundant circuit element. The test circuit (10) generates an output signal (14) indicating that the circuit element selected by the decoder (70) is a redundant circuit element. The output signal (14) is applied to an indicator circuit (16) which is enabled in a test mode by an abnormal condition detector (26). The output (18) of indicator circuit (16) is applied to an external pin (20).

Abstract: A margin test circuit (10) is provided for a semiconductor memory circuit having a plurality of memory cells (16). Each of the memory cells (16) in one row of cells (16) are interconnected to a word line (14). The margin test circuit (10) further includes a row decoder/driver (12) which receives a variable voltage (V.sub.cc *) for changing the signal level stored within a memory cell (16) to thereby determine the marginal voltage level at which the memory cell (16) will maintain storage of a signal level. The variable voltage (V.sub.cc *) is the semiconductor memory circuit main supply source (V.sub.cc) in normal operation but can be forced to a different voltage during the margin test.

Abstract: A circuit (10) is disclosed for use in a semiconductor integrated circuit memory. The integrated circuit memory includes row lines (102-108) which serve to activate the access transistors for memory cells (102a-108a) within the memory circuit. A row decoder circuit (36) receives a plurality of first address bits and produces a drive signal output when the decoder circuit is selected. A transition detector circuit (24) produces a transition signal whenever the state of any of the address bits is changed. A clock decoder circuit receives a plurality of second address bits together with the transition signal to produce a selected clock signal (.phi..sub.A -.phi..sub.D). The combination of the transition signal and the output of the row decoder circuit (36) serves to precharge the gate terminals of the row driver transistors (80-86) for the row lines (102-108). The selected row line receives the active state of the clock signal (.phi..sub.A -.phi..sub.