Abstract: A sense amplifier for use in a serial configuration memory includes multiple stages which are enabled and disabled in a controller manner, in response to a control pulse. The control pulse is produced every Nth period of an externally provided clock signal, the clock being used to clock out a bitstream representing the contents of the memory device. In a preferred embodiment, N such sense amps are utilized to read out in parallel fashion the N memory cells (bits) that constitute an accessed memory location. The sense amps are therefore active only of a period of time sufficient to read out a memory cell.

Abstract: A serial configuration memory device comprises an architecture wherein the reading out of data and the outputting of the bitstream are performed in pipeline fashion. As a result, the device is capable of outputting a bitstream based solely on the frequency of an externally provided clock, and is not limited by the slower operating speed of the sense amp circuitry. A caching scheme is provided which allows the first byte to be pre-loaded during a reset cycle so that the device can immediately begin outputting the bitstream as soon as the reset cycle completes. In a preferred embodiment of the invention, the bitstream consists of serially accessed memory locations starting from memory location zero. In one variation, the bitstream can begin from a memory location other than memory location zero.

Abstract: A power-on-reset circuit includes a first charging stage for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means for charging up a second charging stage. When the second charging stage reaches a first voltage level, a circuit is tripped to pull the potential of the first to ground. The grounding of the first charging stage is fed back to the charging means which shuts off its power burning components and maintains the first voltage level at the second charging stage.

Abstract: An SRAM configures its bitline load structure to implement one of three different precharge schemes, none of which use an ATD circuit. The SRAM monitors its WRITE/READ pin and initiates a first precharging scheme when the SRAM is in a read mode. In the first precharging scheme, every complementary bitline pair is directly coupled to Vcc via a first pmos transistor which is permanently turned on, regardless of whether a memory cell is being read or not. Additionally, both true and false bitlines in every complementary bitline pair are coupled together via a pmos transistor as long as the SRAM remains in a read mode. When in a write mode, the second precharging scheme is initiated causing the second pmos transistor to be turned off and only the first pmos transistors remain active. Thus, all complementary bitline pairs which are not selected for a write operation are pulled up to Vcc by the first pmos transistors.

Abstract: A zero power fuse circuit includes a latch means having two inputs, a first input being latched to ground and a second input being latched to V.sub.cc. The latch means is triggered either by a momentary contact of the first input to ground or by the momentary contact of the second input to V.sub.cc. A first embodiment includes two fuse element/capacitor pairs each coupled to one of the two inputs of the latch means. A second embodiment includes a pull-up transistor and a fuse element/capacitor pair, coupled to the first and second inputs respectively. A third embodiment includes a pull-down transistor and a fuse element/capacitor pair respectively coupled to the second and first inputs of the latch means.

Abstract: A non-volatile programmable circuit having programming and read bitlines, a non-volatile memory cell, and a read select transistor, and a method for its operation. The non-volatile memory cell is programmable through the programming bitline. The read select transistor is connected between the non-volatile memory cell and the read bitline. During read operation, the programming bitline is grounded and programmed information is readable onto the read bitline. During programming operation, the read bitline is grounded, and programmed information is programmable into the non-volatile memory cell for storage and retention.

Abstract: A high voltage circuit includes a first switching device for supplying one of a high voltage (V.sub.pp) and a low voltage (V.sub.cc) to a controlled path that includes a series connection of a control p-channel transistor and a protection p-channel transistor. A high voltage detector is utilized to determine whether V.sub.pp or V.sub.cc is applied to the controlled path. The high voltage detector also establishes a protecting condition for the protection p-channel transistor during V.sub.pp operation. On the other hand, the detector establishes a non-protecting condition during V.sub.cc operation, thereby rendering the protecting p-channel transistor transparent to circuit performance. A signal input switches the control p-channel transistor between on and off states.

Abstract: A protection circuit includes a first controlled path for discharging negative ESD pulses introduced at a signal node. The first controlled path is from the signal node to V.sub.cc via the source and drain electrodes of a first transistor. The gate of the transistor is at a soft ground by connection of the gate through a resistor and an inverter to a fixed voltage supply potential (V.sub.cc). A second controlled path discharges positive ESD pulses via source and drain regions of serially connected second and third transistors to ground. The second transistor has a gate tied at V.sub.cc by means of a resistor and inverter to ground. The third transistor is at soft ground by means of a resistor and inverter to V.sub.cc. The third transistor is turned on by a positive voltage exceeding the threshold voltage of the third transistor, but the second transistor prevents damage to the third transistor by limiting the voltage applied to the third transistor.

Abstract: A non-volatile, low, and zero power, high speed self-sensing programmable device and architecture including a non-volatile self-sensing cell. The non-volatile self-sensing cell is connected out of the speed path of the programmable device, permitting rapid, non-volatile programming and reading operations to be conducted. According to one version, two self-sensing cells are provided with a means for selecting one of the cells for programming or read operation. Each non-volatile self-sensing cell includes a latch having cross-coupled, pull-up transistors and non-volatile pull-down cells. The cross-coupled pull-up transistors are field effect transistors having gates which are connected to the opposite sources of the cross-coupled pull-up transistors.

Abstract: A method is provided for testing a non-programmable non-volatile memory which does not require the writing or erasing of any cells and permits the testing of all normal memory cells. Testing occurs from the device I/O pins and is useful in cases where EPROM memory cells have been bulk erased and placed within an ultraviolet-opaque package. The non-volatile memory is of the type having memory banks of rows and columns. Each bank must have address decoders and means for changing addresses between banks. A separate auxiliary cell or row of cells in a state different from the non-programmed state is provided. An address is supplied for the auxiliary cells and then for the normal cells and the interval between addressing the normal cells and the appearance of an output signal is measured and compared with a predetermined fixed limit. If the limit is exceeded, the address is identified as that of a weak cell whose speed does not meet product specifications.

Abstract: A gas cooking range of the smooth top type has four burners positioned under a single plate of heat-resistant glass/ceramic material; and a single igniter and safety control assembly is centrally positioned between the burners. The supply of gas to each of the burners flows through an ignition chamber where it is ignited, and it then flows through a combustion tube to a combustion chamber, where combustion is completed. Some air is mixed with the gas at the fuel supply control valve, and additional air is supplied through the ignition chamber. The burning gas mixture then flows through the combustion tube to the combustion chamber at the entrance of which an additional quantity of air is added to provide the remainder of air necessary for complete combustion.

Abstract: A gas cooking range of the smooth top type has four burners positioned under a single plate of heat-resistant glass/ceramic material; and a single igniter and safety control assembly is centrally positioned between the burners. The supply of gas to each of the burners flows through an ignition chamber where it is ignited, and it then flows through a combustion tube to a combustion chamber, where combustion is completed. Some air is mixed with the gas at the fuel supply control valve, and additional air is supplied through the ignition chamber. The burning gas mixture then flows through the combustion tube to the combustion chamber at the entrance of which an additional quantity of air is added to provide the remainder of air necessary for complete combustion.

Abstract: A gas cooking range of the smooth top type has four burners positioned under a single plate of heat-resistant glass/ceramic material; and a single igniter and safety control assembly is centrally positioned between the burners. The supply of gas to each of the burners flows through an ignition chamber where it is ignited, and it then flows through a combustion tube to a combustion chamber, where combustion is completed. Some air is mixed with the gas at the fuel supply control valve, and additional air is supplied through the ignition chamber. The burning gas mixture then flows through the combustion tube to the combustion chamber at the entrance of which an additional quantity of air is added to provide the remainder of air necessary for complete combustion.