Abstract: False transitions resulting from capacitive coupling between parallel interconnects driven by dynamic circuits are reduced by classifying interconnects based on the timing of expected data transitions in the signals they carry. Interconnects carrying signals expected to transition during a first portion of a processor cycle are treated as one category, while interconnects carrying signals expected to transition during a second, different portion of the processors cycle are treated as a second category. Interconnects of different categories are interdigitated, a resets of dynamic driving circuits are tuned so that, at any given time, alternate interconnects are “quiet” or stable. Therefore interconnects being driven with data transitions are directly adjacent to quiet lines, and foot devices are implemented as necessary to prevent coupling expected during the reset phase.

Abstract: An adder (300) generates encoded outputs to conserve power. In particular, the adder provides "B2" encoded outputs which only drive one bit per every two bits at a time on conductive lines in a data processing system. A binary input is encoded by an encoder (800, 304) to generate a plurality of bits. The plurality of bits are concatenated to form a plurality of sum values. A portion of the plurality of sum values are then selectively output in response to a logic value of a carry kill signal, a carry generate signal, and a carry propagate signal.