Abstract: Surfaces defined by Bézier tetrahedron are generated on programmable graphics hardware. Custom programmed vertex processing, performed by either the CPU or the GPU includes the computation of a symmetric tensor and the assignment of the unique elements of the computed symmetric tensor as vertex attribute data. The vertex attribute data is interpolated by the graphics hardware and output to custom programmed pixel processing. The pixel processing uses the interpolated vertex attribute data to reconstruct, at each pixel, the symmetric tensor which enables the determination of the roots of the polynomial defining the surface to be generated. If no real roots exist, the pixel processing can exit early. If the roots of the polynomial exist, the smallest root can be used as the basis for computing a normal to a point on the surface being rendered, enabling the determination of the color and depth of that pixel.

Abstract: A method for providing a 16-bit floating point data representation where the 16-bit floating point data representation may be operated upon by a microprocessors native floating point instruction set. The method contemplates the use a variety of techniques for converting the 16-bit floating point number into a representative native floating point value. Thereafter, the native microprocessor floating point instruction set may perform operations upon the converted data. Upon completion, the native floating point data representation may be converted back into the 16-bit floating point value.

Abstract: Surfaces defined by Bézier tetrahedron are generated on programmable graphics hardware. Custom programmed vertex processing, performed by either the CPU or the GPU includes the computation of a symmetric tensor and the assignment of the unique elements of the computed symmetric tensor as vertex attribute data. The vertex attribute data is interpolated by the graphics hardware and output to custom programmed pixel processing. The pixel processing uses the interpolated vertex attribute data to reconstruct, at each pixel, the symmetric tensor which enables the determination of the roots of the polynomial defining the surface to be generated. If no real roots exist, the pixel processing can exit early. If the roots of the polynomial exist, the smallest root can be used as the basis for computing a normal to a point on the surface being rendered, enabling the determination of the color and depth of that pixel.

Abstract: Image data processing and image rendering methods and systems whereby images are displayed on display devices having pixels with separately controllable pixel sub-components. Image data, such as data encoded in a three-channel signal, is passed through a low-pass filter to remove frequencies higher than a selected cutoff frequency, which obtain samples from the color components of the signal that map spatially different image regions to individual pixel sub-components. It has been found that color aliasing effects can be significantly reduces at a cutoff frequency somewhat higher than the Nyquist frequency, while enhancing the spatial resolution of the image. The image data is then passed through sampling filters, A generalized set of filters includes nine filters, one for each combination of one color and one pixel sub-component.

Abstract: Image data processing and image rendering methods and systems whereby images are displayed on display devices having pixels with separately controllable pixel sub-components. Image data, such as data encoded in a three-channel signal, is passed through a low-pass filter to remove frequencies higher than a selected cutoff frequency, which obtain samples from the color components of the signal that map spatially different image regions to individual pixel sub-components. It has been found that color aliasing effects can be significantly reduces at a cutoff frequency somewhat higher than the Nyquist frequency, while enhancing the spatial resolution of the image. The image data is then pass through sampling filters, A generalized set of filters includes nine filters, one for each combination of one color and one pixel sub-component.

Abstract: An optimal filter kernel, formed by convolving a box filter with a filter of fixed integer width and unity area, is used to perform image resizing and reconstruction. The optimal filter has forced zeros at locations along a frequency scale corresponding to the reciprocal of the spacing of one or more pixels that comprise a source image to be resized. When a rescale value for a source image is selected, the optimal filter kernel is computed, mapped to the source image, and centered upon a location within the source image corresponding to the position of an output pixel to be generated. The number of pixels that lie underneath the optimal filter kernel is established by multiplying the number of pixels that comprise the width of the source image by the selected rescale value. Upon mapping the optimal filter kernel, the output pixel values that comprise the resized image are then evaluated by processing the one or more source image pixels, such as through interpolation.

Abstract: An optimal filter kernel, formed by convolving a box filter with a filter of fixed integer width and unity area, is used to perform image resizing and reconstruction. The optimal filter has forced zeros at locations along a frequency scale corresponding to the reciprocal of the spacing of one or more pixels that comprise a source image to be resized. When a rescale value for a source image is selected, the optimal filter kernel is computed, mapped to the source image, and centered upon a location within the source image corresponding to the position of an output pixel to be generated. The number of pixels that lie underneath the optimal filter kernel is established by multiplying the number of pixels that comprise the width of the source image by the selected rescale value. Upon mapping the optimal filter kernel, the output pixel values that comprise the resized image are then evaluated by processing the one or more source image pixels, such as through interpolation.

Abstract: A method for providing a 16-bit floating point data representation where the 16-bit floating point data representation may be operated upon by a microprocessors native floating point instruction set. The method contemplates the use a variety of techniques for converting the 16-bit floating point number into a representative native floating point value. Thereafter, the native microprocessor floating point instruction set may perform operations upon the converted data. Upon completion, the native floating point data representation may be converted back into the 16-bit floating point value.

Abstract: A method for pulling (extracting) a matte of an image of a foreground object from a composite image, using a computer. An image of the foreground object is recorded over at least two backgrounds having arbitrarily different coloring. Each point of one background must have a color that is different than the color of a corresponding point in the other backgrounds. The images may be recorded with an analog camera and digitized with a scanner or recorded with a digital camera. Images should be registered during recording and digitization to eliminate misalignment of corresponding points in each recorded image. A triangulation of corresponding points of each recorded image is performed so that an alpha value (opacity) and a set of color coordinates for each point of an uncomposited image of the foreground object may be determined using either a difference of sums technique or a least squares technique. To facilitate the triangulation, images are recorded of each background alone, without the foreground object.

Abstract: An image generator takes graphical objects and an occlusion relationship for the objects and resolves non-binary occlusion cycles with image compositing operations to produce an output image of the objects. The image generator takes an occlusion relationship for objects in a scene and a set of antialiased image layers with transparency of the objects and produces an antialiased image of the objects with hidden surfaces eliminated. One implementation operates on subsets of the objects in a scene that form non-binary cycles. This implementation uses a chain of atop operators to combine occluding objects with a selected object from a subset, and then combines this result with other objects in the cycle using over image operations. Another implementation computes a chain of out image operations for each object to combine the image layers of the occluding objects with the image layer of the object. The results of each chain of out image operations are summed to produce an output image.

Abstract: A method for simulating fog in 3D graphics rendering applications correctly computes fogged pixel colors even in graphics scenes where two surfaces overlap and the frontmost surface is partially transparent. The method computes the fog for each surface according to the following formula: ƒF atop A, where ƒ is the amount of fog, F is the color of the fog, and A is the color of the pixel being fogged. Each fogged surface can be rendered independently to a separate image layer, called a fogged image layer. The graphics rendering system can then simulate the motion of a fogged image layer by moving the fogged layer in an (x,y) plane without re-computing the fogged pixels, or by moving the fogged layer in the z-direction and independently re-computing the moving fogged layer with a new value for the amount of fog applied to the image layer.

Abstract: A scaling multiplier circuit in accordance with the invention includes a multiplier circuit, a carry calculation circuit, a logic circuit, and an adder circuit. The multiplier circuit produces a 16-bit product of two 8-bit input numbers. The 16-bit product has bits m(15:0). The carry calculation circuit produces a first carryout bit from a sum of a first number consisting of bits m(6:0), a second number consisting of bits m(14:8), and a third number consisting of bit m(7). The logic circuit produces intermediate carryout bits from a sum of bit m(7m), m(15), the first carryout bit, and a constant bit having a value of "1". The adder circuit produces the actual scaled product by summing the intermediate carryout bits and a fourth number consisting of bits m(15:8).