Abstract: A digital phase lock circuit wherein both the phase and frequency of an output signal are synchronized to an input signal. The present phase lock circuit is comprised of a clock signal source, first, second, and third counters, and a holding register. The first counter is utilized to count a predetermined number of cycles of the input signal to establish a first time period. The second counter receives as another input the clock signal and counts the clocks during the established first time period. The value of counted clocks contained in the second counter at the end of the first time period is divided by the predetermined number of cycles the first counter is set to count, and the result is stored in the holding register. The count in the holding register is used to preset the third counter which is then allowed to count down to zero, at the clock rate. The third counter is preset to the value contained in the holding register at each establishment of the first time period.

Abstract: In order to detect the eminent reception of a valid bit serial message, a preamble constituting a string of predetermined number of clock pulses only is employed. Prior to detection of the preamble, each clock and data pulse from the raw data stream is applied to the increment input of a resettable counter. Each clock pulse is also used to trigger a monostable multivibrator which issues a pulse approximating three-fourths of a cell period. This pulse is ANDed with the next subsequent data period, and if a data "1" bit is detected, the satisfied condition is used to reset the counter. Thus, the counter can only reach a terminal count if a valid preamble is received. When the counter attains its terminal count, a latch flip-flop is set and a resultant "separation enable" signal issues to activate straightforward logic for separating the incoming clock and data pulses.