Patents by Inventor James Guyer
James Guyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11983414Abstract: A drive subset matrix is created with at least N+1 drives each having N*N same-size subdivisions. Conceptually, N submatrices are created along with spares equivalent to at least one drive of storage capacity. The spares are located such that every drive has an equal number of spares +/?1. One protection group is located in a lowest indexed subdivision of each of the submatrices. Members of other protection groups are located by selecting members in round robin order and placing each selected member in a free subdivision having a lowest drive index and lowest subdivision index. The drive subset can be grown, split, and reorganized to restore balanced and efficient distribution of spares.Type: GrantFiled: July 19, 2022Date of Patent: May 14, 2024Inventors: Kuolin Hua, Kunxiu Gao, James Guyer
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Publication number: 20240028212Abstract: A drive subset matrix is created with at least N+1 drives each having N*N same-size subdivisions. Conceptually, N submatrices are created along with spares equivalent to at least one drive of storage capacity. The spares are located such that every drive has an equal number of spares +/?1. One protection group is located in a lowest indexed subdivision of each of the submatrices. Members of other protection groups are located by selecting members in round robin order and placing each selected member in a free subdivision having a lowest drive index and lowest subdivision index. The drive subset can be grown, split, and reorganized to restore balanced and efficient distribution of spares.Type: ApplicationFiled: July 19, 2022Publication date: January 25, 2024Applicant: Dell Products L.P.Inventors: Kuolin Hua, Kunxiu Gao, James Guyer
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Patent number: 11720164Abstract: A data storage system with multi-core processors dynamically enables and disables processor cores in order to manage power consumption while maintaining performance. One or more active processor cores are disabled responsive to determining that the current workload can be serviced with fewer active processor cores than are currently enabled while maintaining performance. One or more inactive processor cores are enabled responsive to determining that the current workload cannot be serviced with the currently active processor cores while maintaining performance. Separate utilization thresholds may be implemented for enabling inactive processor cores and disabling active processor cores to promote stability.Type: GrantFiled: April 21, 2022Date of Patent: August 8, 2023Assignee: Dell Products L.P.Inventors: Matthew Fredette, James Guyer
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Patent number: 11675664Abstract: A storage controller has an operating system (OS) and power control firmware configured to manage use of battery power during a power outage event. The OS specifies to the power control firmware first and second sets of physical components that should be shed by power control firmware during a two-phase vault process. Upon a power failure, the power control firmware turns off power to the first set of physical components and notifies the OS of the power failure. The OS determines whether to abort or continue the vault process. If the OS aborts the vault process, the power control firmware restores power to the first set of physical components. If the OS continues the vault process, the power control firmware turns off power to the second set of physical components, the OS saves application state, and moves all data from volatile memory to persistent memory.Type: GrantFiled: August 7, 2021Date of Patent: June 13, 2023Assignee: Dell Products, L.P.Inventors: James Guyer, Richard Boyle, John Burroughs, Clifford Lim, Michael Salerno, Jr
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Publication number: 20230043379Abstract: A storage controller has an operating system (OS) and power control firmware configured to manage use of battery power during a power outage event. The OS specifies to the power control firmware first and second sets of physical components that should be shed by power control firmware during a two-phase vault process. Upon a power failure, the power control firmware turns off power to the first set of physical components and notifies the OS of the power failure. The OS determines whether to abort or continue the vault process. If the OS aborts the vault process, the power control firmware restores power to the first set of physical components. If the OS continues the vault process, the power control firmware turns off power to the second set of physical components, the OS saves application state, and moves all data from volatile memory to persistent memory.Type: ApplicationFiled: August 7, 2021Publication date: February 9, 2023Inventors: James Guyer, Richard Boyle, John Burroughs, Clifford Lim, Michael Salerno, JR.
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Patent number: 11176063Abstract: A system may include a plurality processing cores for processing I/O operations and at least one interconnect component for communicatively coupling one or more external components to the plurality of processing cores. The at least one interconnect component may be directly physically connected to each of the plurality of processing cores. The interconnect component may route I/O operations to one of the processing cores based on a memory range of the I/O operation. An I/O communication including an I/O operation may be received at the interconnect component. The memory address range of the I/O operation may be determined. A processing core corresponding to the determined memory address range of the I/O operation may be determined, for example, by accessing a data structure that maps address ranges to processing cores. An I/O communication including the I/O operation may be sent from the interconnect component to the determined processing core.Type: GrantFiled: November 1, 2019Date of Patent: November 16, 2021Assignee: EMC IP Holding Company LLCInventor: James Guyer
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Patent number: 11144454Abstract: Metadata in volatile memory is selectively compressed and destaged to non-volatile storage in the event of an emergency shutdown due to loss of like power. Compression offload hardware that is normally used for data compression is used to compress the metadata, e.g. at line speed. The compressed metadata and any uncompressed metadata that was not selected for compression may be destaged to vault drives along with compressed and uncompressed data that is in the volatile memory. Compression during vaulting may decrease power consumption when operating under standby battery power.Type: GrantFiled: November 22, 2019Date of Patent: October 12, 2021Assignee: Dell Products L.P.Inventors: James Guyer, Jason Duquette
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Patent number: 11122121Abstract: A storage system includes four storage engines, each storage engine including two compute nodes. Eight point-to-point connections are used to interconnect pairs of compute nodes on different storage engines, such that each compute node is connected to exactly two other compute nodes of the storage system. Atomic operations can be initiated by any compute node on any other compute node. Atomic operations received by a compute node on one of the point-to-point connections will be forwarded on the other point-to-point connection if the atomic operation is not directed to the compute node. During normal operation, atomic operations on a given compute node are performed on a host adapter associated with the compute node. Upon failure of the host adapter associated with the compute node, atomic operations may be performed on the compute node using the host adapter of the other compute node of the storage engine.Type: GrantFiled: November 22, 2019Date of Patent: September 14, 2021Assignee: EMC IP Holding Company LLCInventors: James Guyer, Alesia Tringale, Jason Duquette, William Baxter
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Patent number: 11086379Abstract: Power conservation logic for a storage node operates in parallel with an emergency shutdown process in which an emergency power source is engaged and data and metadata are destaged from volatile memory to non-volatile managed drives. The power conservation logic serially implements power conservation actions until enough reserve power is available to complete the emergency shutdown process. The power conservation logic may learn how much power savings are realized from each conservation action and adjust the order in which the conservation actions are serially implemented, e.g. in order from greatest to least power consumption reduction.Type: GrantFiled: October 28, 2019Date of Patent: August 10, 2021Assignee: EMC IP HOLDING COMPANY LLCInventors: James Guyer, Clifford Lim, Scott Gordon
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Publication number: 20210157726Abstract: Metadata in volatile memory is selectively compressed and destaged to non-volatile storage in the event of an emergency shutdown due to loss of like power. Compression offload hardware that is normally used for data compression is used to compress the metadata, e.g. at line speed. The compressed metadata and any uncompressed metadata that was not selected for compression may be destaged to vault drives along with compressed and uncompressed data that is in the volatile memory. Compression during vaulting may decrease power consumption when operating under standby battery power.Type: ApplicationFiled: November 22, 2019Publication date: May 27, 2021Applicant: EMC IP HOLDING COMPANY LLCInventors: James Guyer, Jason Duquette
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Publication number: 20210157487Abstract: A storage system includes four storage engines, each storage engine including two compute nodes. Eight point-to-point connections are used to interconnect pairs of compute nodes on different storage engines, such that each compute node is connected to exactly two other compute nodes of the storage system. Atomic operations can be initiated by any compute node on any other compute node. Atomic operations received by a compute node on one of the point-to-point connections will be forwarded on the other point-to-point connection if the atomic operation is not directed to the compute node. During normal operation, atomic operations on a given compute node are performed on a host adapter associated with the compute node. Upon failure of the host adapter associated with the compute node, atomic operations may be performed on the compute node using the host adapter of the other compute node of the storage engine.Type: ApplicationFiled: November 22, 2019Publication date: May 27, 2021Inventors: James Guyer, Jason Duquette, Alesia Tringale, Sean Pollard, Julie Zhivich, Jinxian Xian, William Baxter
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Publication number: 20210160316Abstract: A storage system includes four storage engines, each storage engine including two compute nodes. Eight point-to-point connections are used to interconnect pairs of compute nodes on different storage engines, such that each compute node is connected to exactly two other compute nodes of the storage system. Atomic operations can be initiated by any compute node on any other compute node. Atomic operations received by a compute node on one of the point-to-point connections will be forwarded on the other point-to-point connection if the atomic operation is not directed to the compute node. During normal operation, atomic operations on a given compute node are performed on a host adapter associated with the compute node. Upon failure of the host adapter associated with the compute node, atomic operations may be performed on the compute node using the host adapter of the other compute node of the storage engine.Type: ApplicationFiled: November 22, 2019Publication date: May 27, 2021Inventors: James Guyer, Alesia Tringale, Jason Duquette, William Baxter
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Publication number: 20210133122Abstract: A system may include a plurality processing cores for processing I/O operations and at least one interconnect component for communicatively coupling one or more external components to the plurality of processing cores. The at least one interconnect component may be directly physically connected to each of the plurality of processing cores. The interconnect component may route I/O operations to one of the processing cores based on a memory range of the I/O operation. An I/O communication including an I/O operation may be received at the interconnect component. The memory address range of the I/O operation may be determined. A processing core corresponding to the determined memory address range of the I/O operation may be determined, for example, by accessing a data structure that maps address ranges to processing cores. An I/O communication including the I/O operation may be sent from the interconnect component to the determined processing core.Type: ApplicationFiled: November 1, 2019Publication date: May 6, 2021Applicant: EMC IP Holding Company LLCInventor: James Guyer
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Publication number: 20210124405Abstract: Power conservation logic for a storage node operates in parallel with an emergency shutdown process in which an emergency power source is engaged and data and metadata are destaged from volatile memory to non-volatile managed drives. The power conservation logic serially implements power conservation actions until enough reserve power is available to complete the emergency shutdown process. The power conservation logic may learn how much power savings are realized from each conservation action and adjust the order in which the conservation actions are serially implemented, e.g. in order from greatest to least power consumption reduction.Type: ApplicationFiled: October 28, 2019Publication date: April 29, 2021Applicant: EMC IP HOLDING COMPANY LLCInventors: James Guyer, Clifford Lim, Scott Gordon
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Patent number: 10853280Abstract: A storage system includes a storage engine having a first compute node, a second compute node, a first fabric adapter, and a second fabric adapter, the first compute node having a first memory and the second compute node having a second memory. The first compute node is connected to both the first and second fabric adapters, and the second compute node is connected to both the second and first fabric adapters. Both fabric adapters are configured to perform atomic operations on a memory of its respective compute node, and each fabric adapter contains a multi-initiating module configured to enable both the first compute node and the second compute node to initiate memory access operations on its respective memory.Type: GrantFiled: November 22, 2019Date of Patent: December 1, 2020Assignee: EMC IP Holding Company LLCInventors: James Guyer, Jason Duquette, Alesia Tringale, Julie Zhivich
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Patent number: 10705905Abstract: Selective use of a software path and hardware path help to provide fine-grained T10-PI support while maintaining IO operation efficiency for single IO read/write commands transferring multiple data segments. NVMe hardware capability (i.e. the hardware path) is always utilized for CPU-intensive CRC verification. NVMe hardware capability is utilized for application tag and reference tag verification whenever possible. Software running on a computing node (i.e. the software path) is used for application tag and reference tag verification and replacement when those functions cannot be implemented by the NVMe hardware.Type: GrantFiled: October 30, 2018Date of Patent: July 7, 2020Assignee: EMC IP HOLDING COMPANY LLCInventors: Ningdong Li, Stephen Ives, Seema Pai, Scott Rowlands, James Guyer
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Publication number: 20200133764Abstract: Selective use of a software path and hardware path help to provide fine-grained T10-PI support while maintaining IO operation efficiency for single IO read/write commands transferring multiple data segments. NVMe hardware capability (i.e. the hardware path) is always utilized for CPU-intensive CRC verification. NVMe hardware capability is utilized for application tag and reference tag verification whenever possible. Software running on a computing node (i.e. the software path) is used for application tag and reference tag verification and replacement when those functions cannot be implemented by the NVMe hardware.Type: ApplicationFiled: October 30, 2018Publication date: April 30, 2020Applicant: EMC IP HOLDING COMPANY LLCInventors: Ningdong Li, Stephen Ives, Seema Pai, Scott Rowlands, James Guyer
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Patent number: 8595416Abstract: A method, computer program product, and computing system for identifying a low-write-frequency portion of a solid-state storage device. If it is determined that the low-write-frequency portion is of sufficient size to function as over-provisioning space for the solid-state storage device, the low-write-frequency portion is utilized as over-provisioning space.Type: GrantFiled: March 31, 2011Date of Patent: November 26, 2013Assignee: EMC CorporationInventors: Patrick J. Weiler, James Guyer
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Patent number: 7821922Abstract: A packet switching network having a plurality of nodes and a network having: a plurality of switches couples to the nodes and links interconnecting ports of the plurality of switches. Each one of the switches has a normal routing table for routing packets from a source one of the nodes to a destination one of the nodes through the network in according to the normal routing table and, for, upon such upon such source one of the nodes detecting a fault in transmission of such packet, routing such to a predetermined designated fault one of the ports of such switch.Type: GrantFiled: March 31, 2006Date of Patent: October 26, 2010Assignee: EMC CorporationInventors: John K. Walton, Kendell Chilton, James Guyer
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Publication number: 20050071556Abstract: A system interface having a plurality of directors, one portion of such directors being adapted for coupling to a host computer/server and another portion of the directors being adapted for coupling to a bank of disk drives. The plurality of directors are interconnected through a network. A common resource section is provided having a resource shared among the plurality of directors. The common shared resource section includes a shared computer code used by the plurality of directors. The code includes computer code for booting up each one of the plurality directors. The common shared code storage section is interconnected to the directors through the network. A second, redundant common shared resource section is provided. The network is a packet switching network.Type: ApplicationFiled: September 30, 2003Publication date: March 31, 2005Inventors: John Walton, William Baxter, Kendell Chilton, Daniel Castel, Michael Bermingham, James Guyer