Abstract: A digital storage element comprises a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. The master and slave transparent latches have opposite transparent polarities when in a functional mode and have the same polarities (e.g., positive level sense) when in a scan mode. The transparent polarity of a transparent latch defines the state of a clock to that latch for which the transparent latch is transparent.

Abstract: A sigma-delta converter having dynamic dithering that reduces or removes idle-channel tones and increase linearity of the converter. The dither is differentiated in multiple orders before being applied to the converter quantizer. The differentiation order and the amplitude of the dither are determined dynamically based on the input signal amplitude in order to obtain the most effectiveness of dithering. The dynamic dither can be used in both analog-to-digital and digital-to-analog converters.

Abstract: Disclosed is a circuit and method for reducing output swing in a sigma delta modulator. The quantizer output swing reduction circuit and method of the present invention advantageously enables the modulator to have a larger input/output swing range without degrading the SNR and SFDR performance. One embodiment of the present invention comprises a conventional sigma-delta modulation circuit (100) and a quantizer swing reduction block (210). The quantizer swing reduction block (210) comprises an input signal Vx (216), a signal processing block (214) with transfer function H3 and another signal processing block (215) with transfer function H2*H3.

Abstract: The present invention accepts timing and clock signals with a desired frequency and undesired duty cycle CLKIN, and outputs a clock signal CLKOUT with the desired frequency and desired duty cycle. If the clock signal is known to have a duty cycle of greater than 50%, one exemplary embodiment of the present invention delays the rising edge of the clock signal so as to produce a clock signal with a 50% duty cycle. One exemplary embodiment of the present invention comprises a charge pump integrator (102) configured in a feedback loop, the output of the charge pump integrator (102) operable as a controlling node to delay inverter (115). If the clock signal CLKIN at the input of the circuit has a duty cycle of greater than 50%, then the charge pump integrator (102) will, through PBIAS, cause delay inverter 115 to delay of the rising edge of CLKIN through delay inverter (115). The charge pump integrator, through PBIAS, drives the duty cycle of the clock signal towards 50%.