Patents by Inventor James J. Demarest
James J. Demarest has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11113533Abstract: A computer-implemented method executed by a processor for reducing exposure of a plurality of objects to environmental conditions by employing a smart room tracking system is presented. The computer-implemented method includes counting a number of individuals within a space including the plurality of objects via one or more image capture devices and determining whether each individual makes direct eye contact with any of the plurality of objects by evaluating orientation, posture, and eye movement of each individual. The computer-implemented method further includes shielding, via an object viewing controller, an object of the plurality of objects from view when no direct eye contact is determined and making an object of the plurality of objects viewable, via the object viewing controller, when direct eye contact is determined.Type: GrantFiled: September 17, 2019Date of Patent: September 7, 2021Assignee: International Business Machines CorporationInventors: Marc A. Bergendahl, Christopher J. Penny, James J. Demarest, Christopher Waskiewicz, Jean Wynne, Jonathan Fry
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Patent number: 10566414Abstract: A backend-of-the-line (BEOL) semiconductor capacitor made by method, apparatus, or computer program product, through an airgap metallization process, patterning a first electrode by removing a portion of inter-layer dielectric for a desired capacitor area, depositing a dielectric for a capacitor insulator, filling the desired capacitor area to form a second electrode, polishing and capping the second electrode, and interconnecting the first electrode and the second electrode.Type: GrantFiled: September 1, 2016Date of Patent: February 18, 2020Assignee: International Business Machines CorporationInventors: Marc A. Bergendahl, James J. Demarest, Christopher J. Penny, Christopher Waskiewicz
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Patent number: 10546813Abstract: A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the adjacent metal lines. A second level is formed including at least one dielectric layer atop the first level. A plurality of trench structures is formed in the at least on dielectric layer. At least one of the plurality of trench structures opens the air gap. A conductive material is formed within the trenches. The conductive material deposited in the open air gap provides a vertical fuse.Type: GrantFiled: April 18, 2018Date of Patent: January 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Marc A. Bergendahl, James J. Demarest, Christopher J. Penny, Christopher J. Waskiewicz
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Publication number: 20200026924Abstract: A computer-implemented method executed by a processor for reducing exposure of a plurality of objects to environmental conditions by employing a smart room tracking system is presented. The computer-implemented method includes counting a number of individuals within a space including the plurality of objects via one or more image capture devices and determining whether each individual makes direct eye contact with any of the plurality of objects by evaluating orientation, posture, and eye movement of each individual. The computer-implemented method further includes shielding, via an object viewing controller, an object of the plurality of objects from view when no direct eye contact is determined and making an object of the plurality of objects viewable, via the object viewing controller, when direct eye contact is determined.Type: ApplicationFiled: September 17, 2019Publication date: January 23, 2020Inventors: Marc A. Bergendahl, Christopher J. Penny, James J. Demarest, Christopher Waskiewicz, Jean Wynne, Jonathan Fry
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Patent number: 10528817Abstract: A computer-implemented method executed by a processor for reducing exposure of a plurality of objects to environmental conditions by employing a smart room tracking system is presented. The computer-implemented method includes counting a number of individuals within a space including the plurality of objects via one or more image capture devices and determining whether each individual makes direct eye contact with any of the plurality of objects by evaluating orientation, posture, and eye movement of each individual. The computer-implemented method further includes shielding, via an object viewing controller, an object of the plurality of objects from view when no direct eye contact is determined and making an object of the plurality of objects viewable, via the object viewing controller, when direct eye contact is determined.Type: GrantFiled: December 12, 2017Date of Patent: January 7, 2020Assignee: International Business Machines CorporationInventors: Marc A. Bergendahl, Christopher J. Penny, James J. Demarest, Christopher Waskiewicz, Jean Wynne, Jonathan Fry
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Patent number: 10475878Abstract: A backend-of-the-line (BEOL) semiconductor capacitor made by method, apparatus, or computer program product, through an airgap metallization process, patterning a first electrode by removing a portion of inter-layer dielectric for a desired capacitor area, depositing a dielectric for a capacitor insulator, filling the desired capacitor area to form a second electrode, polishing and capping the second electrode, and interconnecting the first electrode and the second electrode.Type: GrantFiled: December 28, 2017Date of Patent: November 12, 2019Assignee: International Business Machines CorporationInventors: Marc A. Bergendahl, James J. Demarest, Christopher J. Penny, Christopher Waskiewicz
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Patent number: 10453793Abstract: A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the adjacent metal lines. A second level is formed including at least one dielectric layer atop the first level. A plurality of trench structures is formed in the at least on dielectric layer. At least one of the plurality of trench structures opens the air gap. A conductive material is formed within the trenches. The conductive material deposited in the open air gap provides a vertical fuse.Type: GrantFiled: August 2, 2018Date of Patent: October 22, 2019Assignee: International Business Machines CorporationInventors: Marc A. Bergendahl, James J. Demarest, Christopher J. Penny, Christopher J. Waskiewicz
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Publication number: 20190180106Abstract: A computer-implemented method executed by a processor for reducing exposure of a plurality of objects to environmental conditions by employing a smart room tracking system is presented. The computer-implemented method includes counting a number of individuals within a space including the plurality of objects via one or more image capture devices and determining whether each individual makes direct eye contact with any of the plurality of objects by evaluating orientation, posture, and eye movement of each individual. The computer-implemented method further includes shielding, via an object viewing controller, an object of the plurality of objects from view when no direct eye contact is determined and making an object of the plurality of objects viewable, via the object viewing controller, when direct eye contact is determined.Type: ApplicationFiled: December 12, 2017Publication date: June 13, 2019Inventors: Marc A. Bergendahl, Christopher J. Penny, James J. Demarest, Christopher Waskiewicz, Jean Wynne, Jonathan Fry
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Patent number: 10319676Abstract: Embodiments are directed to a method and resulting structures for forming a semiconductor device having a vertically integrated nanosheet fuse. A nanosheet stack is formed on a substrate. The nanosheet stack includes a semiconductor layer formed between an upper nanosheet and a lower nanosheet. The semiconductor layer is modified such that an etch rate of the modified semiconductor layer is greater than an etch rate of the upper and lower nanosheets when exposed to an etchant. Portions of the modified semiconductor layer are removed to form a cavity between the upper and lower nanosheets and a silicide region is formed in the upper nanosheet.Type: GrantFiled: March 16, 2018Date of Patent: June 11, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robin H. Chao, James J. Demarest, Nicolas J. Loubet
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Patent number: 10319677Abstract: A vertical fuse element, including, a conductive silicide base on a surface of a substrate, and a conductive silicide pillar extending in a direction perpendicular to the surface of the substrate, where the conductive silicide pillar is on the conductive silicide base, and wherein the conductive silicide pillar includes an upper portion having a width, W5, a base having a width, W6, and a neck region having a width, W7, where W7<W5, and W7?W6.Type: GrantFiled: May 30, 2018Date of Patent: June 11, 2019Assignee: International Business Machines CorporationInventors: Kangguo Cheng, James J. Demarest, Juntao Li
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Publication number: 20190167226Abstract: An infant gastrointestinal monitor and a method for infant gastrointestinal monitoring are provided. The infant gastrointestinal monitor includes a belly band for placing around at least a midsection area of a subject infant. The infant gastrointestinal monitor further includes a plurality of wireless sound sensors, integrated with the belly band in an array configuration, for identifying a location of a gastrointestinal noise in the subject infant based on cross-referencing signals from the plurality of wireless sound sensors. He infant gastrointestinal monitor also includes a controller, operatively coupled to the plurality of wireless sound sensors, for analyzing the location and one or more other parameters of the gastrointestinal noise to identify a probable cause of the noise and a recommended action for a caregiver to alleviate an underlying condition causing the noise.Type: ApplicationFiled: December 4, 2017Publication date: June 6, 2019Inventors: Jean Wynne, Marc A. Bergendahl, Jonathan Fry, Christopher Waskiewicz, Christopher J. Penny, James J. Demarest
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Patent number: 10170548Abstract: A semiconductor device and process of making the same generally includes simultaneously forming nanosheet capacitors with nanosheet FET devices on the same substrate. The nanosheets in the capacitor have a width and are coupled to one another by sacrificial layers, wherein the sacrificial layers have a width smaller than the nanosheet width, and wherein the nanosheets and the sacrificial layers are conductively coupled to the substrate. The nanosheets in the FET devices are spaced apart and free of sacrificial layers. The nanosheets in the FET device have a width less than half the width of the nanosheets in the capacitor region.Type: GrantFiled: March 21, 2018Date of Patent: January 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, James J. Demarest, John G. Gaudiello, Juntao Li
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Publication number: 20180342458Abstract: A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the adjacent metal lines. A second level is formed including at least one dielectric layer atop the first level. A plurality of trench structures is formed in the at least on dielectric layer. At least one of the plurality of trench structures opens the air gap. A conductive material is formed within the trenches. The conductive material deposited in the open air gap provides a vertical fuse.Type: ApplicationFiled: August 2, 2018Publication date: November 29, 2018Inventors: Marc A. Bergendahl, James J. Demarest, Christopher J. Penny, Christopher J. Waskiewicz
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Publication number: 20180277481Abstract: A vertical fuse element, including, a conductive silicide base on a surface of a substrate, and a conductive silicide pillar extending in a direction perpendicular to the surface of the substrate, where the conductive silicide pillar is on the conductive silicide base, and wherein the conductive silicide pillar includes an upper portion having a width, W5, a base having a width, W6, and a neck region having a width, W7, where W7<W5, and W7?W6.Type: ApplicationFiled: May 30, 2018Publication date: September 27, 2018Inventors: Kangguo Cheng, James J. Demarest, Juntao Li
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Patent number: 10083908Abstract: A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the adjacent metal lines. A second level is formed including at least one dielectric layer atop the first level. A plurality of trench structures is formed in the at least on dielectric layer. At least one of the plurality of trench structures opens the air gap. A conductive material is formed within the trenches. The conductive material deposited in the open air gap provides a vertical fuse.Type: GrantFiled: April 5, 2017Date of Patent: September 25, 2018Assignee: International Business Machines CorporationInventors: Marc A. Bergendahl, James J. Demarest, Christopher J. Penny, Christopher J. Waskiewicz
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Publication number: 20180240752Abstract: A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the adjacent metal lines. A second level is formed including at least one dielectric layer atop the first level. A plurality of trench structures is formed in the at least on dielectric layer. At least one of the plurality of trench structures opens the air gap. A conductive material is formed within the trenches. The conductive material deposited in the open air gap provides a vertical fuse.Type: ApplicationFiled: April 18, 2018Publication date: August 23, 2018Inventors: Marc A. Bergendahl, James J. Demarest, Christopher J. Penny, Christopher J. Waskiewicz
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Publication number: 20180226343Abstract: A vertical fuse element, including, a conductive silicide base on a surface of a substrate, and a conductive silicide pillar extending in a direction perpendicular to the surface of the substrate, where the conductive silicide pillar is on the conductive silicide base, and wherein the conductive silicide pillar includes an upper portion having a width, W5, a base having a width, W6, and a neck region having a width, W7, where W7<W5, and W7?W6.Type: ApplicationFiled: February 6, 2017Publication date: August 9, 2018Inventors: Kangguo Cheng, James J. Demarest, Juntao Li
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Patent number: 10043746Abstract: A vertical fuse element, including, a conductive silicide base on a surface of a substrate, and a conductive silicide pillar extending in a direction perpendicular to the surface of the substrate, where the conductive silicide pillar is on the conductive silicide base, and wherein the conductive silicide pillar includes an upper portion having a width, W5, a base having a width, W6, and a neck region having a width, W7, where W7<W5, and W7?W6.Type: GrantFiled: February 6, 2017Date of Patent: August 7, 2018Assignee: International Business Machines CorporationInventors: Kangguo Cheng, James J. Demarest, Juntao Li
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Patent number: 10043748Abstract: Embodiments are directed to a method and resulting structures for forming a semiconductor device having a vertically integrated nanosheet fuse. A nanosheet stack is formed on a substrate. The nanosheet stack includes a semiconductor layer formed between an upper nanosheet and a lower nanosheet. The semiconductor layer is modified such that an etch rate of the modified semiconductor layer is greater than an etch rate of the upper and lower nanosheets when exposed to an etchant. Portions of the modified semiconductor layer are removed to form a cavity between the upper and lower nanosheets and a silicide region is formed in the upper nanosheet.Type: GrantFiled: November 13, 2017Date of Patent: August 7, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robin H. Chao, James J. Demarest, Nicolas J. Loubet
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Publication number: 20180219066Abstract: A semiconductor device and process of making the same generally includes simultaneously forming nanosheet capacitors with nanosheet FET devices on the same substrate. The nanosheets in the capacitor have a width and are coupled to one another by sacrificial layers, wherein the sacrificial layers have a width smaller than the nanosheet width, and wherein the nanosheets and the sacrificial layers are conductively coupled to the substrate. The nanosheets in the FET devices are spaced apart and free of sacrificial layers. The nanosheets in the FET device have a width less than half the width of the nanosheets in the capacitor region.Type: ApplicationFiled: March 21, 2018Publication date: August 2, 2018Inventors: Kangguo Cheng, James J. Demarest, John G. Gaudiello, Juntao Li