Abstract: A voltage/current regulator supplying controlled current with PVT headroom adjustment. In an example application, an LED backlight driver controls ILED string current, and controls a voltage regulator supplying VOUT string voltage with sufficient headroom voltage VHDRM to supply the ILED string current. The LED driver controls ILED string current with an MLED current control transistor, including gate drive referenced to a reference voltage VREF. VOUT/VHDRM are adjusted for PVT operating conditions by generating a replica/reference current ILED/RATIO (proportional to ILED string current) with a replica current control transistor MLED/RATIO based on VREF. ILED/RATIO is mirrored to a second replica MLED/RATIO transistor that saturates at a PVT_REF reference voltage corresponding to a minimum voltage that can supply the required ILED current (as represented by the ILED/RATIO replica/reference current), accounting for PVT operating conditions.

Abstract: A voltage/current regulator supplying controlled current with PVT headroom adjustment. In an example application, an LED backlight driver controls ILED string current, and controls a voltage regulator supplying VOUT string voltage with sufficient headroom voltage VHDRM to supply the ILED string current. The LED driver controls ILED string current with an MLED current control transistor, including gate drive referenced to a reference voltage VREF. VOUT/VHDRM are adjusted for PVT operating conditions by generating a replica/reference current ILED/RATIO (proportional to ILED string current) with a replica current control transistor MLED/RATIO based on VREF. ILED/RATIO is mirrored to a second replica MLED/RATIO transistor that saturates at a PVT_REF reference voltage corresponding to a minimum voltage that can supply the required ILED current (as represented by the ILED/RATIO replica/reference current), accounting for PVT operating conditions.

Abstract: A voltage controlled oscillator circuit is shown using multiple delay stages with the last stage looped back out of phase to the first stage. Each stage delay is formed by charging one or more capacitors. The circuitry uses active components demonstrating a square law relationship between a control voltage and a resulting current. The current is ultimately used to charge the delay capacitor. The net effect is a linear relationship of the VCO frequency and an input control voltage. The range of the linear relationship is extended by using square law current sources to provide suitable currents that extend the linear range when other active devices are no longer supporting the square law relationship. In addition bipolar device are used to compensate for temperature and batch to batch processing effects of FET devices.

Abstract: A phase locked loop, PLL, is described with multiple parallel charge pumps that are selectively disabled as phase lock is approached. A lock detection circuit is described that enabled reference currents to be fed to the parallel charge pumps. The error signal from a phase detector is arranged as UP and a DOWN signals that are averaged in the lock detector. When the average error is large, all the reference currents feed the charge pumps that provide a high loop gain to reduce the lock time. As the lock becomes closer selective reference currents are disabled to reduce loop gain so that a smooth transition to lock is made. Selectively switching currents into a low pass filter that usually follows a charge pump in a PLL circuit automatically reduces switching noise by the operation of the low pass filter.

Abstract: A current boost circuit that supplies additional current to a voltage reference power rail. When the voltage reference power rail drops due to an excessive current demand from the load, the drop is sensed and a switch is activated supplying additional current to the voltage reference rail. A gain stage is capacitively coupled to the reference voltage and any drop is transferred through this capacitor to a gain stage that amplifies the drop. The amplified drop is capacitively coupled to a solid state switch that turns on connecting an additional current source to the reference voltage rail. The solid state switch is biased just below its turn on threshold.

Abstract: A phase locked loop circuit is used to provide timing clocks for data bit recovery from a serial data flow. The system locks to a SYNC signal, preferably a lower frequency fifty percent duty cycle square wave with a period equal to the time of a fully framed serial data word. When a start signal transition is detected the system is prevented from trying to lock onto the data signal edge transitions. But, the system provides a signal suitable for clocking in the individual data bits.

Abstract: A voltage controlled oscillator circuit is shown using multiple delay stages with the last stage looped back out of phase to the first stage. Each stage delay is formed by charging one or more capacitors. The circuitry uses active components demonstrating a square law relationship between a control voltage and a resulting current. The current is ultimately used to charge the delay capacitor. The net effect is a linear relationship of the VCO frequency and an input control voltage. The range of the linear relationship is extended by using square law current sources to provide suitable currents that extend the linear range when other active devices are no longer supporting the square law relationship. In addition bipolar device are used to compensate for temperature and batch to batch processing effects of FET devices.

Abstract: A phase locked loop, PLL, is described with multiple parallel chnrge pumps that are selectively disabled as phase lock is approached. A lock detection circuit is described that enabled reference currents to be fed to the parallel charge pumps. The error signal from a phase detector is arranged as UP and a DOWN signals that are averaged in the lock detector. When the average error is large, all the reference currents feed the charge pumps that provide a high loop gain to reduce the lock time. As the lock becomes closer selective reference currents are disabled to reduce loop gain so that a smooth transition to lock is made. Selectively switching currents into a low pass filter that usually follows a charge pump in a PLL circuit automatically reduces switching noise by the operation of the low pass filter.

Abstract: A buffer circuit with slow output edges is described. Pulsed higher value currents are driven from one shot timing circuits to inject a pulse of current into the control gate of the buffer's output MOSFET to speed up the beginning of the turning on or the turning off of the output MOSFT. When the beginning and turning on and off is reached lower value current sources continue to drive the gate of the output MOSFET. In one embodiment, one shots are triggered from the rising and falling edges of the input signal. The effect of the higher value current pulses is to reduce the circuit delay through the buffer. Also, the pulse width can be designed as temperature sensitive, and supply voltage sensitive so as to maintain the buffer circuit delay as substantially constant as temperature, supply voltage and process variation occur.

Abstract: A current boost circuit that supplies additional current to a voltage reference power rail. When the voltage reference power rail drops due to an excessive current demand from the load, the drop is sensed and a switch is activated supplying additional current to the voltage reference rail. A gain stage is capacitively coupled to the reference voltage and any drop is transferred through this capacitor to a gain stage that amplifies the drop. The amplified drop is capacitively coupled to a solid state switch that turns on connecting an additional current source to the reference voltage rail. The solid state switch is biased just below its turn on threshold.

Abstract: A phase locked loop circuit is used to provide timing clocks for data bit recovery from a serial data flow. The system locks to a SYNC signal, preferably a lower frequency fifty percent duty cycle square wave with a period equal to the time of a fully framed serial data word. When a start signal transition is detected the system is prevented from trying to lock onto the data signal edge transitions. But, the system provides a signal suitable for clocking in the individual data bits.

Abstract: An automated continuous manufacturing system which includes a rotatable work table having a plurality of work piece supports for maintaining work pieces during operation of said system, and a plurality of work stations for performing cleaning, pretreatment, treatment or assembly tasks on work pieces secured to said work piece supports. Each of the tasks performed at the work table is performed at a respective work station. Certain of the work stations comprise a removable station subassembly for performing a specific task. The removable station subassemblies are removably engagable with the rotatable work table and may be replaced with an alternate removable station subassembly for performing a desired alternate task. One of the work stations is an assembly station engaged with the rotatable work table for receiving work pieces from their individual work piece supports. The assembly station further includes a removing subassembly for removing the work pieces from the work piece supports for further assembly.