Patents by Inventor James Jaussi
James Jaussi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11483186Abstract: A digital transmitter architecture is disclosed to transmit (TX) multi-gigabit per second data signals on single carriers (SC) or orthogonal frequency division multiplexing (OFDM) carriers at millimeter wave frequencies in either one of a high-resolution modulation mode or a spectral shaping mode. The architecture includes a number of digital power amplifier (DPA) and modulation reconfigurable circuit segments to process individual bits of a data bit stream in parallel according to a specific circuit configuration corresponding to the selected TX mode using a multiplexer to switch between configurations.Type: GrantFiled: September 19, 2018Date of Patent: October 25, 2022Assignee: Intel CorporationInventors: Bryan Casper, James Jaussi, Chintan Thakkar, Stefan Shopov
-
Publication number: 20210288035Abstract: Embodiments may relate to a microelectronic package that includes a package substrate with an active bridge positioned therein. An active die may be coupled with the package substrate, and communicatively coupled with the active bridge. A photonic integrated circuit (PIC) may also be coupled with the package substrate and communicatively coupled with the active bridge. Other embodiments may be described or claimed.Type: ApplicationFiled: March 12, 2020Publication date: September 16, 2021Applicant: Intel CorporationInventors: Thomas Liljeberg, Andrew C. Alduino, Ravindranath Vithal Mahajan, Ling Liao, Kenneth Brown, James Jaussi, Bharadwaj Parthasarathy, Nitin A. Deshpande
-
Publication number: 20210168000Abstract: A digital transmitter architecture is disclosed to transmit (TX) multi-gigabit per second data signals on single carriers (SC) or orthogonal frequency division multiplexing (OFDM) carriers at millimeter wave frequencies in either one of a high-resolution modulation mode or a spectral shaping mode. The architecture includes a number of digital power amplifier (DPA) and modulation reconfigurable circuit segments to process individual bits of a data bit stream in parallel according to a specific circuit configuration corresponding to the selected TX mode using a multiplexer to switch between configurations.Type: ApplicationFiled: September 19, 2018Publication date: June 3, 2021Inventors: Bryan Casper, James Jaussi, Chintan Thakkar, Stefan Shopov
-
Patent number: 10923164Abstract: An apparatus is provided which comprises: a first power supply rail to provide a first power supply; second and third power supply rails to provide second and third power supplies, respectively, wherein a voltage level of the first power supply is higher than a voltage level of each of the second and third power supplies; a first driver circuitry coupled to the first power supply rail and the second power supply rail; a second driver circuitry coupled to the third power supply rail, and coupled to the first driver circuitry; and a stack of transistors of N conductivity type coupled to the first power supply rail, and to the second driver circuitry.Type: GrantFiled: September 29, 2018Date of Patent: February 16, 2021Assignee: Intel CorporationInventors: Hariprasath Venkatram, Mohammed G. Mostofa, Rajesh Inti, Roger K. Cheng, Aaron Martin, Christopher Mozak, Pavan Kumar Kappagantula, Hsien-Pao Yang, Mozhgan Mansuri, James Jaussi, Harishankar Sridharan
-
Publication number: 20200105317Abstract: An apparatus is provided which comprises: a first power supply rail to provide a first power supply; second and third power supply rails to provide second and third power supplies, respectively, wherein a voltage level of the first power supply is higher than a voltage level of each of the second and third power supplies; a first driver circuitry coupled to the first power supply rail and the second power supply rail; a second driver circuitry coupled to the third power supply rail, and coupled to the first driver circuitry; and a stack of transistors of N conductivity type coupled to the first power supply rail, and to the second driver circuitry.Type: ApplicationFiled: September 29, 2018Publication date: April 2, 2020Applicant: Intel CorporationInventors: Hariprasath VENKATRAM, Mohammed G. MOSTOFA, Rajesh INTI, Roger K. CHENG, Aaron MARTIN, Christopher MOZAK, Pavan Kumar KAPPAGANTULA, Hsien-Pao YANG, Mozhgan MANSURI, James JAUSSI, Harishankar SRIDHARAN
-
Publication number: 20170235701Abstract: Techniques for embedded high speed serial interface methods are described herein. The techniques include an apparatus for sideband signaling including a first serial sideband link module and a second serial sideband link module. The first serial sideband link module is to propagate packets from an upstream port to a downstream port via a first signaling lane, and the second serial sideband link module is to propagate packets from the downstream port to the upstream port via a second signaling lane.Type: ApplicationFiled: December 24, 2014Publication date: August 17, 2017Applicant: INTEL CORPORATIONInventors: Akshay Pethe, Mahesh Wagh, David Harriman, Su Wei Lim, Debendra Das Sharma, Daniel Froelich, Venkatraman Iyer, James Jaussi, Zuoguo Wu
-
Patent number: 8571513Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.Type: GrantFiled: July 2, 2012Date of Patent: October 29, 2013Assignee: Intel CorporationInventors: Frank O'Mahony, Bryan Casper, James Jaussi, Matthew B. Haycock, Joseph Kennedy, Mozhgan Mansuri, Stephen R. Mooney
-
Publication number: 20120281323Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.Type: ApplicationFiled: July 2, 2012Publication date: November 8, 2012Inventors: Frank O'Mahony, Bryan Casper, James Jaussi, Matthew B. Haycock, Joseph Kennedy, Mozhgan Mansuri, Stephen R. Mooney
-
Patent number: 8213894Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.Type: GrantFiled: December 29, 2005Date of Patent: July 3, 2012Assignee: Intel CorporationInventors: Frank O'Mahony, Bryan Casper, James Jaussi, Matthew B. Haycock, Joseph Kennedy, Mozhgan Mansuri, Stephen R. Mooney
-
Publication number: 20070152746Abstract: A tunable bandpass filter to provide a filtered differential clock signal in response to an input differential clock signal, where an embodiment comprises a transistor pair loaded by tunable loads, and a feedback circuit to tune the tunable loads. In some embodiments, the feedback circuit tunes the loads to maximize a small-signal differential gain. In other embodiments, the feedback circuit tunes the loads to minimize a metric indicative of jitter in the filtered differential clock signal. Other embodiments are described and claimed.Type: ApplicationFiled: December 30, 2005Publication date: July 5, 2007Inventors: Bryan Casper, Timothy Hollis, James Jaussi, Stephen Mooney, Frank O'Mahony, Mozhgan Mansuri
-
Publication number: 20070153445Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.Type: ApplicationFiled: December 29, 2005Publication date: July 5, 2007Inventors: Frank O'Mahony, Bryan Casper, James Jaussi, Matthew Haycock, Joseph Kennedy, Mozhgan Mansuri, Stephen Mooney
-
Publication number: 20070146011Abstract: Disclosed herein are duty cycle adjustment circuits to control the duty cycle in a clock signal. In some embodiments, a circuit is provided comprising a clock driver to drive a differential clock signal through a clock path. A feedback circuit is coupled (i) to the clock path to monitor offset in the clock signal, and (ii) to the clock driver to digitally control the clock driver offset based on the monitored clock signal offset. Other embodiments are disclosed herein.Type: ApplicationFiled: December 28, 2005Publication date: June 28, 2007Inventors: Frank O'Mahony, Bryan Casper, James Jaussi, Moonkyun Maeng
-
Publication number: 20070147491Abstract: According to embodiments of the subject matter disclosed in this application, transmit equalization, systematic jitter correction, and jitter injection may be achieved through a lookup table transmitter equalizer. The equalizer may be a multiple-way interleaving equalizer, with each interleaved section having its own lookup table. Entries in each lookup table may be modified to correct systematic jitters occurring in the received signal. Additionally, random errors may be injected to each lookup table. Injected errors are converted to both amplitude and phase modulation across a channel. By measuring the signal at the receiver, the characteristics of the transmission line may be obtained.Type: ApplicationFiled: December 22, 2005Publication date: June 28, 2007Inventors: Bryan Casper, James Jaussi
-
Publication number: 20070140397Abstract: Alignment of a receiver clock signal with a transmitter clock signal based upon a received data signal is disclosed. Some embodiments generate, based upon of phase bits and valid phase bits, a phase signal having a voltage level selected from at least three voltage levels. One voltage level corresponds to shifting the receiver clock signal in a first direction. Another voltage level corresponds to shifting the receiver clock signal in a second direction. The other voltage level corresponds to repeating a previous shift of the receiver clock signal.Type: ApplicationFiled: December 21, 2005Publication date: June 21, 2007Inventors: James Jaussi, Sriram Venkataraman, Bryan Caspar
-
Publication number: 20070115048Abstract: In some embodiments, equalizer circuits with controllably variable offsets at their outputs are provided.Type: ApplicationFiled: November 7, 2005Publication date: May 24, 2007Inventors: Mozhgan Mansuri, Frank O'Mahony, Bryan Casper, James Jaussi
-
Publication number: 20070064787Abstract: In some embodiments disclosed herein, equalizers in a receiver are adapted during normal operation, as they extract bit data from a received bit stream, to account for channel and/or circuit fluctuations.Type: ApplicationFiled: September 21, 2005Publication date: March 22, 2007Inventors: James Jaussi, Bryan Casper, Ganesh Balamurugan, Stephen Mooney
-
Publication number: 20060291552Abstract: In some embodiments, a circuit is provided that comprises a decision feedback equalizer to receive a bit stream signal. The equalizer comprises a summing circuit having a first input to receive a cursor bit sample from the bit stream, a second input to receive a first cursor bit signal, and an output to provide a cursor bit output signal corresponding to the cursor bit sample with at least some postcursor distortion removed therefrom. Other embodiments are disclosed and/or claimed herein.Type: ApplicationFiled: June 22, 2005Publication date: December 28, 2006Inventors: Evelina Yeung, Sanjay Dabral, James Jaussi, Alok Tripathi
-
Publication number: 20060226881Abstract: A delay-locked loop (DLL) architecture is provided that includes a voltage controlled delay line, a sample-and-hold circuit and an amplifier circuit. The voltage controlled delay line may have a plurality of buffer stages to provide a first clock signal and a second clock signal. The sample-and-hold circuit may receive signals corresponding to the first clock signal and the second clock signal. The sample-and-hold circuit may provide two sampled signals based on the received signals. Additionally, the amplifier circuit may be coupled to the sample-and-hold circuit and the voltage controlled delay line. The amplifier circuit may provide a control voltage to the buffer stages of the voltage controlled delay line based on the sampled signals received from the sample-and-hold circuit.Type: ApplicationFiled: April 12, 2005Publication date: October 12, 2006Inventors: James Jaussi, Randy Mooney
-
Publication number: 20060140324Abstract: A global clock recovery circuit and port circuit determine and combine static phase adjustment information and dynamic phase adjustment information for multiple data signals. Static phase adjustment information is determined for each of the multiple data signals, and dynamic phase adjustment information is determined in common for the multiple data signals.Type: ApplicationFiled: December 29, 2004Publication date: June 29, 2006Inventors: Bryan Casper, Aaron Martin, Stephen Mooney, James Jaussi
-
Publication number: 20060049845Abstract: In one embodiment, a decision feedback equalizer helps mitigate intersymbol interference in a bi-directional signaling environment. In the particular embodiment, the decision feedback equalizer includes a voltage-to-current converter to source a received differential current to first and second node, a latch to provide logic signal when comparing currents sourced to the first and second nodes, a memory unit to store the logic signals, and a mapping circuit to source first and second feedback currents to the first and second nodes. This embodiment further includes a transmitter to transmit data over a transmission line during receiving, and a digital-to-analog converter to provide a differential current to the first and second nodes to substantially cancel that part of the received differential currents contributed by the transmitter.Type: ApplicationFiled: September 8, 2004Publication date: March 9, 2006Inventors: James Jaussi, Bryan Casper