Abstract: A three-dimensional memory array device can include mid-plane terrace regions between a pair of memory array regions. The electrically conductive layers of the three-dimensional memory array device continuously extend between the pair of memory array regions through a connection region, which is provided adjacent to the mid-plane terrace regions. Contact via structures contacting the electrically conductive layers can be provided in the mid-plane terrace regions, and through-memory-level via structures that extend through the alternating stack and connected to underlying lower metal interconnect structures and semiconductor devices can be provided through the mid-plane terrace region and/or through the connection region. Upper metal interconnect structures can connect the contact via structures and the through-memory-level via structures.

Abstract: A three-dimensional memory device includes driver transistors containing boron doped semiconductor active regions, device contact via structures in physical contact with the boron doped semiconductor active regions, the device contact via structures containing at least one of tantalum, tungsten, and cobalt, and a three-dimensional memory array located over the driver transistors and including an alternating stack of insulating layers and electrically conductive layers and memory structures vertically extending through the alternating stack.

Abstract: A trench having a uniform depth is provided in an upper portion of a semiconductor substrate. A continuous dielectric material layer is formed, which includes a gate dielectric that fills an entire volume of the trench. A gate electrode is formed over the gate dielectric such that the gate electrode overlies a center portion of the gate dielectric and does not overlie a first peripheral portion and a second peripheral portion of the gate dielectric that are located on opposing sides of the center portion of the gate dielectric. After formation of a dielectric gate spacer, a source extension region and a drain extension region are formed within the semiconductor substrate by doping respective portions of the semiconductor substrate.

Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.

Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.

Abstract: A three-dimensional memory array device can include mid-plane terrace regions between a pair of memory array regions. The electrically conductive layers of the three-dimensional memory array device continuously extend between the pair of memory array regions through a connection region, which is provided adjacent to the mid-plane terrace regions. Contact via structures contacting the electrically conductive layers can be provided in the mid-plane terrace regions, and through-memory-level via structures that extend through the alternating stack and connected to underlying lower metal interconnect structures and semiconductor devices can be provided through the mid-plane terrace region and/or through the connection region. Upper metal interconnect structures can connect the contact via structures and the through-memory-level via structures.

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a semiconductor substrate. Memory openings are formed through the alternating stack. An optional silicon-containing epitaxial pedestal and a memory film are formed in each memory opening. After forming an opening through a bottom portion of the memory film within each memory opening, a germanium-containing semiconductor layer and a dielectric layer is formed in each memory opening. Employing the memory film and the dielectric layer as a crucible, a liquid phase epitaxy anneal is performed to convert the germanium-containing semiconductor layer into a germanium-containing epitaxial channel layer. A dielectric core and a drain region can be formed over the dielectric layer. The germanium-containing epitaxial channel layer is single crystalline, and can provide a higher charge carrier mobility than a polysilicon channel.

Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.

Abstract: A trench having a uniform depth is provided in an upper portion of a semiconductor substrate. A continuous dielectric material layer is formed, which includes a gate dielectric that fills an entire volume of the trench. A gate electrode is formed over the gate dielectric such that the gate electrode overlies a center portion of the gate dielectric and does not overlie a first peripheral portion and a second peripheral portion of the gate dielectric that are located on opposing sides of the center portion of the gate dielectric. After formation of a dielectric gate spacer, a source extension region and a drain extension region are formed within the semiconductor substrate by doping respective portions of the semiconductor substrate.

Abstract: A three-dimensional stacked memory device is configured to provide uniform programming speeds of different sets of memory strings formed in memory holes. In a process for removing sacrificial material from word line layers, a block oxide layer in the memory holes is etched away relatively more when the memory hole is relatively closer to an edge of the word line layers where an etchant is introduced. A thinner block oxide layer is associated with a faster programming speed. To compensate, memory strings at the edges of the word line layers are programmed together, separate from the programming of interior memory strings. A program operation can use a higher initial program voltage for programming the interior memory strings compared to the edge memory strings.

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers. Vertical NAND strings are formed through the alternating stack, each of which includes a drain region, memory cell charge storage transistors, and a pair of drain select transistors in a series connection. A common bit line is electrically connected to drain regions of two vertical NAND strings. The drain select transistors of the two vertical NAND strings are configured such that drain select transistors sharing a first common drain select gate electrode provide a higher threshold voltage for one of the two vertical NAND strings, and drain select transistors sharing a second common drain select gate electrode provide a higher threshold voltage for the other of the two vertical NAND strings. The different threshold voltages can be provided by a combination of a masked ion implantation and selective charge injection.

Abstract: A layer stack including an alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of memory stack structures, backside trenches are formed through the layer stack. The sacrificial material layers are replaced with electrically conductive layers. Drain select level dielectric isolation structures are formed through drain select level of the stack after formation of the electrically conductive layers. The drain select level dielectric isolation structures laterally separate portions of conductive layers that are employed as drain select level gate electrodes for the memory stack structures.

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

Abstract: Apparatus and methods are disclosed for selecting one or more mobile device applications using context data describing the current environment of a mobile device and application metadata describing environment conditions where applications are more likely to be relevant, in order to improve the experience of discovering, downloading, and installing mobile device applications. According to one embodiment, a method comprises associating metadata with mobile device applications automatically receiving context data representing a current geographical location from a mobile phone, searching the metadata to determine which applications are likely of interest based on the current geographical location, and transmitting notification data to the mobile phone indicating the determined applications.

Abstract: A three-dimensional memory device including self-aligned drain select level electrodes is provided. Memory stack structures extend through an alternating stack of insulating layers and spacer material layers. Each of the memory stack structures includes a memory film and a memory level channel portion. Drain select level channel portions are formed over the memory level channel portions with respective lateral shifts with respect to underlying memory stack structures. The direction of lateral shifts alternates from row to row for each row of drain select level channel portions. Drain select level gate dielectrics and drain select level gate electrodes are formed on the drain select level channel portions. Each drain select level gate electrode controls two rows of drain select level channel portions, and is laterally spaced from neighboring drain select level gate electrodes.

Abstract: Sacrificial semiconductor material portions are connected by a sacrificial semiconductor line extending along a different horizontal direction and protruding into an underlying source conductive layer. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through the sacrificial semiconductor material portions. A backside trench can be formed through the vertically alternating stack employing the sacrificial semiconductor line as an etch stop structure. Source strap material portions providing lateral electrical contact to semiconductor channels of the memory stack structures can be formed by replacement of sacrificial semiconductor material portions and the sacrificial semiconductor line with source strap material portions. Structural-reinforcement portions may be employed to provide structural stability during the replacement process.

Abstract: The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.

Abstract: A three-dimensional memory device includes driver transistors containing boron doped semiconductor active regions, device contact via structures in physical contact with the boron doped semiconductor active regions, the device contact via structures containing at least one of tantalum, tungsten, and cobalt, and a three-dimensional memory array located over the driver transistors and including an alternating stack of insulating layers and electrically conductive layers and memory structures vertically extending through the alternating stack.

Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.

Abstract: A three-dimensional memory device including self-aligned drain select level electrodes is provided. Memory stack structures extend through an alternating stack of insulating layers and spacer material layers. Each of the memory stack structures includes a memory film and a memory level channel portion. Drain select level channel portions are formed over the memory level channel portions with respective lateral shifts with respect to underlying memory stack structures. The direction of lateral shifts alternates from row to row for each row of drain select level channel portions. Drain select level gate dielectrics and drain select level gate electrodes are formed on the drain select level channel portions. Each drain select level gate electrode controls two rows of drain select level channel portions, and is laterally spaced from neighboring drain select level gate electrodes.