Patents by Inventor James L. Buie

James L. Buie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4546456
    Abstract: A read-only memory circuit having, for a given memory access time, a power requirement of approximately one half of the power requirement needed to allow for a worst-case condition in which all bit storage locations may be in a binary memory state requiring maximum power consumption. Information stored in each row of the memory circuit is selectively complemented to minimize the power consumption in the individual rows and columns. Tables are used to store complement indicators for the rows and columns, and decoding circuitry selectively complements data read from the memory circuit, in accordance with the stored complement indicators.
    Type: Grant
    Filed: June 8, 1983
    Date of Patent: October 8, 1985
    Assignee: TRW Inc.
    Inventor: James L. Buie
  • Patent number: 3981072
    Abstract: A thick layer of silicon dioxide is grown on a semiconductive substrate and then etched to form an elongated opening that defines the outer boundaries of a diffused transistor. The thick silicon dioxide layer serves as a permanent fixed, diffusion mask. The first diffusion is performed through the permanent mask opening. Thereafter, portions of the elongated opening are masked by secondary thin layers of silicon dioxide or photo-resist, and subsequent diffusions are performed through different unmasked portions of the elongated opening.
    Type: Grant
    Filed: December 6, 1974
    Date of Patent: September 21, 1976
    Assignee: TRW Inc.
    Inventor: James L. Buie