Abstract: A spatial light modulator (10) having a micromechanical active portion (12) encompassed by a light shield (14). The light shield (14) is fabricated upon a substrate (36) and has a plurality of openings (72, and 80) to permit underlying layers of photoresist (90, 92) to be undercut from beneath the light shield. Removal of the photoresist layers provides a sufficiently flat light shield, and eliminates the possibility that particles from the photoresist layer could migrate to beneath active micromirrors (30) of the spatial light modulator (12).

Abstract: A method of testing a large integrated circuit (10) of modular design. Test equipment is connected to a dedicated testing pad section (20) for each circuit section (22, 24, 34) of each module (12, 14, 16). The circuit section under test is tested via the testing pad adjacent that circuit section. The test equipment is then stepped to the testing section for the next circuit section. When testing is completed, the testing section is then electrically isolated from the circuit sections to prevent interference with operation of the entire circuit (10).

Abstract: An array of individual elements (10) having reduced control circuitry as compared to existing devices. Sets of elements (11) share a memory cell (12), such that each memory cell (12) has the same fanout as other memory cells (12). Each element (11) in a set is switched to an on or off state via a reset line (13) that is separate from that of the other elements (11) in that set. Data is loaded in split bit-frames during a set time period, such that each split bit-frame contains only the data for elements (11) on one reset line (13). Thus, the same memory cell (12) can be used to deliver data to all elements (11) in its fanout because only one element (11) in the fanout is switched at a time.

Abstract: The spatial light modulator (30) of the DMD type having associated memory cells (10) with a single bit line memory read back architecture (54). The memory cells (10) include a charge equalization switch (50) comprising a transistor connected across the bit lines (16,18) of the memory cell (10). This charge equalization transistor (50) is momentarily turned on (T.sub.3) to balance residual charge on the memory cell bit lines (16,18), after a write cycle (T.sub.2) but before the read cycle (T.sub.4). When the memory cell contents are subsequently read (T.sub.4), the memory cell contents will not change state. A single amplifier (54) is connected to one bit line for reading the memory cell contents. The single bit line (18) memory read back architecture provides a more efficient circuit layout to the spacing constraints required with DMDs, consumes less power than designs with a differential amplifier, and additionally, provides yield improvements.

Abstract: A digital micro-mirror device (20) for imaging applications, having an array (21) of mirror elements for forming the image, and having data loading circuitry (22, 23) for loading data for addressing the mirror elements. The data loading circuitry (22, 23) has a row of shift registers (23), which receive data and pass the data to latches (22). Each output of the shift registers (23) is connected to a number of latches (22). For loading a row of data, the row is divided into portions, and the shift registers (23) receive the row of data in sequential portions. It delivers each portion to a different set of latches, each set comprised of a latch from each shift register output. Each set of latches holds its portion of the row of data on bit-lines while the remaining portions of the row are input to the shift registers (23) and passed to other sets of latches (22).

Abstract: A monolithic DMD spatial light modulator (20) including a storage cell array (24) of charge storage elements (30). Each charge storage cell (30) is formed using robust MOS processes, and comprises a pair of capacitors (32) having a polysilicon electrode fabricated over a substrate, and separated by a thin oxide dielectric. Each capacitor (32) is shielded by several light impermeable metal shields (37, 64, 66, 68, 72, 74, 80, 82, 88) to prevent discharging due to light incident to SLM (20). The substrate electrode (38) is encompassed by an n+ doped region (42) providing a source of minority carriers to an inversion region under the polysilicon electrode (50).

Abstract: A large integrated circuit (10) of modular design, each module (12,14,16) having a circuit section (22,24,34) and a separate dedicated testing pad section (20). Each circuit module (12,14,16) can be individually functionally tested as an independent circuit with conventional prober equipment for defects. Each testing pad section (20) facilitates controlling the entire integrated circuit (10) so that the respective module circuit section (12,14,16) can be tested. Control circuitry (26) comprised of pass gates is provided to isolate the testing pad sections (20) from the operational portion (22,24,34) of the integrated circuit (10) when not under test. The present invention is ideally suited for large spatial light modulators, memory devices and other large sophisticated integrated circuits.

Abstract: A digital motor controller (17) for controlling both the phase and speed of a brushless DC motor (16). An error detection unit (21) detects a speed error or a phase error. An error logic unit (22) uses the error to determine a speed control value, that is proportional to represent an average motor input voltage that varies from the current input voltage by an amount determined by the error. A pulse width modulation unit (23) receives the speed control value and uses it to determine the duty cycle for the motor drive signals. A commutation unit (24) modulates the appropriate drive signal, and a drive stage (27) delivers the drive signals to the motor (16).

Abstract: A method and device for controlling the bias voltages for a split-reset spatial light modulator. Each block of the spatial light modulator can be individually controlled lowering the throughput needed to load each frame of data. Blocks are selected individually or in groups with the potential of providing one voltage condition on the selected blocks and a different voltage condition on the deselected blocks. One embodiment of the disclosed method comprises input latches and buffers 44, address decode logic 46 to determine the selected blocks, mode select logic 48 to determine the requested operation, delay circuitry 50 to minimize current loading, and level shifters 52 to convert logic signals to voltage levels appropriate to control the output drive circuitry 54.

Abstract: A digital micro-mirror device (20) for imaging applications, having an array (21) of mirror elements for forming the image and data loading circuitry (22, 23, 24) for loading data for addressing the mirror elements. The data loading circuitry (22, 23, 24) has a row of shift registers (24), which receive one row of data at a time, which they deliver to latches (23). The latches (23) hold the data on bit-lines, which run down columns of the array (21). The row to be loaded is selected with a row decoder (25). A block load circuit (22), comprised of a shift register (35) and logic gates (33) divides each row of memory cells into blocks (31) and ensures that each block of a row of memory cells is sequentially loaded.

Abstract: A method and device for controlling the bias voltages for a split-reset spatial light modulator. Each block of the spatial light modulator can be individually controlled lowering the throughput needed to load each frame of data. Blocks are selected individually or in groups with the potential of providing one voltage condition on the selected blocks and a different voltage condition on the deselected blocks. One embodiment of the disclosed method comprises input latches and buffers 44, address decode logic 46 to determine the selected blocks, mode select logic 48 to determine the requested operation, delay circuitry 50 to minimize current loading, and level shifters 52 to convert logic signals to voltage levels appropriate to control the output drive circuitry 54.

Abstract: A spatial light modulator (10) having reduced control circuitry as compared to existing devices. Sets of pixel elements (11) share a memory cell (12), such that each memory cell (12) has the same fanout as other memory cells (12). Each pixel element (11) in a set is switched to an on or off state via a reset line (13) that is separate from that of the other pixel elements (11) in that set. Frame data is loaded in split bit-frames during a set time period, such that each split bit-frame contains only the data for pixel elements (11) on one reset line (13). Thus, the same memory cell (12) can be used to deliver data to all pixel elements (11) in its fanout because only one pixel element (11) in the fanout is switched at a time.