Abstract: A voltage stress testable embedded dual capacitor structure for use in an integrated circuit (IC). The voltage stress testable embedded dual capacitor structure includes a semiconductor substrate with an electrically insulating base layer thereon, a first embedded dual capacitor and a second embedded dual capacitor connected in series and disposed on the electrically insulating base layer, and a probe pad. The probe pad is electrically connected directly to the first and second embedded dual capacitors at a location therebetween (e.g. by being connected to an electrically conductive top plate of the second embedded dual capacitor). The voltage stress testable embedded dual capacitor structure can be voltage stress tested using an applied voltage high enough to assure the reliability of the first and second embedded dual capacitors, without exposing other electronic devices in the IC to a damaging level of voltage. Also provided is a process for voltage stress testing embedded dual capacitors.

Abstract: A multi-chip packaging arrangement that contemplates stacking discrete components over film based components is disclosed. The multi-chip package includes a substrate having one or more film based components formed thereon. A discrete component is mounted on the substrate over the film based component such that it is electrically isolated from the film based component. One or more die components are also mounted on the substrate and a plurality of leads are provided for electrically connecting the multi-chip package to external circuitry. Wiring traces formed on the substrate are provided to electrically connect various ones of the components and the leads. A packaging material is provided to encapsulate the components and the wiring traces and leaves a portion of the leads exposed to facilitate electrically connecting the multi-chip package to external circuitry. Methods of making such multi-chip packages are also disclosed.