Abstract: Systems and methods are presented for allocating resources. In particular, the systems and methods may receive and process a requested SP state to identify for first SP channel information regarding (i) signal processing resources required and (ii) state priority, based on a first state table defining for each of a plurality of states for the first SP channel information regarding signal processing resources required and state priority information; and based on the identified information, arbitrating as between a current state and a requested state. Systems and methods are also provided for fast blanking override of a requested signal processing (SP) state. In particular, the systems and methods may receive a blanking input and automatically override a requested SP state for a first SP channel based on using a first state table to determine blank susceptibility information for the requested SP state.

Abstract: Systems and methods are presented for allocating resources. In particular, the systems and methods may receive and process a requested SP state to identify for first SP channel information regarding (i) signal processing resources required and (ii) state priority, based on a first state table defining for each of a plurality of states for the first SP channel information regarding signal processing resources required and state priority information; and based on the identified information, arbitrating as between a current state and a requested state. Systems and methods are also provided for fast blanking override of a requested signal processing (SP) state. In particular, the systems and methods may receive a blanking input and automatically override a requested SP state for a first SP channel based on using a first state table to determine blank susceptibility information for the requested SP state.

Abstract: Systems and methods are presented for allocating resources. In particular, the systems and methods may receive and process a requested SP state to identify for first SP channel information regarding (i) signal processing resources required and (ii) state priority, based on a first state table defining for each of a plurality of states for the first SP channel information regarding signal processing resources required and state priority information; and based on the identified information, arbitrating as between a current state and a requested state. Systems and methods are also provided for fast blanking override of a requested signal processing (SP) state. In particular, the systems and methods may receive a blanking input and automatically override a requested SP state for a first SP channel based on using a first state table to determine blank susceptibility information for the requested SP state.

Abstract: A redundancy scrubber. The novel scrubber includes fault detection logic for detecting if a circuit has been upset and a mechanism for automatically rewriting data to the circuit when an upset is detected. In an illustrative embodiment, the scrubber corrects for upsets in a circuit comprised of a plurality of redundant circuits, each redundant circuit including a data port for receiving data and a load enable port for controlling when the redundant circuit should load new data. The fault detection logic processes the outputs from each of the redundant circuits and outputs a fault detect signal indicating whether an upset has been detected in one or more of the redundant circuits. The fault detect signal is coupled to the load enable ports, forcing the redundant circuits to immediately reload with corrected data from a voter or with new incoming data when an upset is detected.

Abstract: A redundancy scrubber. The novel scrubber includes fault detection logic for detecting if a circuit has been upset and a mechanism for automatically rewriting data to the circuit when an upset is detected. In an illustrative embodiment, the scrubber corrects for upsets in a circuit comprised of a plurality of redundant circuits, each redundant circuit including a data port for receiving data and a load enable port for controlling when the redundant circuit should load new data. The fault detection logic processes the outputs from each of the redundant circuits and outputs a fault detect signal indicating whether an upset has been detected in one or more of the redundant circuits. The fault detect signal is coupled to the load enable ports, forcing the redundant circuits to immediately reload with corrected data from a voter or with new incoming data when an upset is detected.

Abstract: A data encoder. The novel encoder includes a first circuit for generating a fundamental sequence coded data stream from an incoming input data stream, a second circuit for generating a k-split data stream from the incoming data stream, and a third circuit for combining the fundamental sequence coded data stream and k-split data stream to form a final encoded output. The first circuit includes a circuit for converting the incoming input data stream into a novel intermediate format comprising a set bit word and a zero word count, and a zero-word expander for converting the intermediate format to the fundamental sequence coded data stream. The first circuit may also include a register adapted to store the intermediate format to provide rate buffering.

Abstract: A data encoder. The novel encoder includes a first circuit for generating a fundamental sequence coded data stream from an incoming input data stream, a second circuit for generating a k-split data stream from the incoming data stream, and a third circuit for combining the fundamental sequence coded data stream and k-split data stream to form a final encoded output. The first circuit includes a circuit for converting the incoming input data stream into a novel intermediate format comprising a set bit word and a zero word count, and a zero-word expander for converting the intermediate format to the fundamental sequence coded data stream. The first circuit may also include a register adapted to store the intermediate format to provide rate buffering.

Abstract: A method and apparatus for storing memory modeling data (20) in computer memory (76). The memory modeling data (20) is converted into an X-data value (36) according to a first mapping scheme (32). The first mapping scheme (32) associates the value of each digit of the memory modeling data (20) with a predetermined digit which has one of three values. The X-data value (36) is partitioned into subgroups (52). A character is mapped to each of the subgroups (52) according to a second mapping scheme (64). The mapped characters (60) are stored in computer memory (76).

Abstract: A memory speed testing circuit including a memory addressing circuit (11, 13, 15) for sequentially providing to the address input of the memory device a binary address A and a binary address A which is a binary 1's complement of the binary address A, wherein the binary address A is provided within a selected time interval after the provision of the binary address A when the memory device is in a read mode; a data circuit (21, 23, 24) for generating a first binary test word and a second binary test word that is a 1's complement of the first binary test word; wherein the first binary test word is input to the data port of the memory device when the binary address A is provided the address input of the memory device when the memory device is in the write mode, and wherein the second binary test word is input to the data port of the memory device when the binary address A is provided to the address input of the memory device when the memory device is in the write mode; and a comparator (25) for comparing the firs

Abstract: A feed through circuit for an integrated circuit, including a first I/O pad (39); an input buffer (37) having an input connected to the first I/O pad and having an output; a second I/O pad (19); and an output buffer (15) having an input that is connected to the output of the input buffer and not connected to core logic circuitry of the integrated circuit, and further having an output that is connected to the second I/O pad; whereby a signal on the first I/O pad is fed through to the second I/O pad.

Abstract: A digital input circuit including a first digital buffer for receiving a digital data signal and for providing a first buffered digital data output, the first digital buffer having a first switching threshold voltage; a second digital buffer for receiving the digital data signal and for providing a second buffered digital data output, the second digital buffer having a second switching threshold voltage that is greater than the first predetermined switching threshold voltage; a selection circuit responsive to the first buffered digital data output and the second buffered digital data output for providing a selection circuit output that is a replica of the first buffered digital data output or the second buffered digital data output; and a flip-flop for receiving the selection means output and providing a flip-flop output that is indicative of the logical state of the digital data signal.

Abstract: A digital counter which can be easily and thoroughly tested with a short sequence of random or pseudo-random input vectors. The counter includes a pair of pseudo-random input generators, probability regeneration logic and full scale observability logic. The counter has improved capability to detect stuck at faults in the counter full scale output gates. The counter is particularly advantageous in a VLSI circuit design.