Abstract: A voltage regulator system of an information handling system includes a Smart Power Stage (SPS) and a voltage regulator controller. The SPS includes a high-side transistor and a low-side transistor. The voltage regulator controller detects a normal power down of the information handling system and sets bleed state for the SPS to a first state. Based on the bleed state being set to the first state, the voltage regulator controller provides a first control voltage to the low-side transistor and a second control voltage to the high-side transistor. The first control voltage causes the low-side transistor to be fully turned on, and the second control voltage causes the high-side transistor to be in a linear region. In response to a predetermined amount of time expiring, the voltage regulator controller enters the SPS in an idle mode.

Abstract: An interface apparatus for installing an add-in module to an information handling system includes the add-in module and an add-in module socket. The add-in module includes a card-edge connector on a first edge of the add-in module, and an electrical contact finger on a second edge of the add-in module. The add-in module socket is affixed to the information handling system and receives the add-in module. The add-in module socket includes a card-edge connector interface for receiving the card edge connector, and a slot channel for receiving the second edge of the add-in module. The slot channel includes an electrical contact pad configured such that, when the add-in module is installed into the add-in module socket, a current is provided between the add-in module socket and the add-in module through the electrical contact pad and the electrical contact finger.

Abstract: An interface apparatus for installing memory modules to an information handling system includes a riser card and an adapter. The riser card includes a first card-edge connector on a first edge of the riser card, and a second card-edge connector on a second edge of the riser card. The first card-edge connector is associated with a first interface and the second card-edge connector is associated with a second interface. The adapter includes a first socket on a first side of the adapter, and a second socket on a second side of the adapter opposite to the first side. The first socket and the second socket are associated with the second interface. The first socket is configured to receive the second card-edge connector of the riser card. The second socket is configured to receive a memory module.

Abstract: An interface apparatus for installing an add-in module to an information handling system includes the add-in module and an add-in module socket. The add-in module includes a card-edge connector on a first edge of the add-in module, and an electrical contact finger on a second edge of the add-in module. The add-in module socket is affixed to the information handling system and receives the add-in module. The add-in module socket includes a card-edge connector interface for receiving the card edge connector, and a slot channel for receiving the second edge of the add-in module. The slot channel includes an electrical contact pad configured such that, when the add-in module is installed into the add-in module socket, a current is provided between the add-in module socket and the add-in module through the electrical contact pad and the electrical contact finger.

Abstract: An information handling system includes an identification resistor, calibration circuitry, and a system-on-a-chip (SOC). The SOC sets the calibration line to a first digital state to place the calibration circuitry in an inventory mode. While the calibration circuitry is in the inventory mode, the SOC determines an inventory amount of time to charge the capacitor to a voltage substantially equal to a threshold voltage. The SOC then sets the calibration line to a second digital state to place the calibration circuitry in a calibration mode. While the calibration circuitry is in the calibration mode, the SOC determines a calibration amount of time to charge the capacitor to the voltage substantially equal to the threshold voltage. The SOC determines a resistance of the identification resistor based on the inventory amount of time and the calibration amount of time. The SOC also determines bit strapping information corresponding to the determined resistance.

Abstract: An information handling system includes an identification resistor, calibration circuitry, and a system-on-a-chip (SOC). The SOC sets the calibration line to a first digital state to place the calibration circuitry in an inventory mode. While the calibration circuitry is in the inventory mode, the SOC determines an inventory amount of time to charge the capacitor to a voltage substantially equal to a threshold voltage. The SOC then sets the calibration line to a second digital state to place the calibration circuitry in a calibration mode. While the calibration circuitry is in the calibration mode, the SOC determines a calibration amount of time to charge the capacitor to the voltage substantially equal to the threshold voltage. The SOC determines a resistance of the identification resistor based on the inventory amount of time and the calibration amount of time. The SOC also determines bit strapping information corresponding to the determined resistance.

Abstract: An information handling system includes an identification resistor, calibration circuitry, and a system-on-a-chip (SOC). The SOC sets the calibration line to a first digital state to place the calibration circuitry in an inventory mode. While the calibration circuitry is in the inventory mode, the SOC determines an inventory amount of time to charge the capacitor to a voltage substantially equal to a threshold voltage. The SOC then sets the calibration line to a second digital state to place the calibration circuitry in a calibration mode. While the calibration circuitry is in the calibration mode, the SOC determines a calibration amount of time to charge the capacitor to the voltage substantially equal to the threshold voltage. The SOC determines a resistance of the identification resistor based on the inventory amount of time and the calibration amount of time. The SOC also determines bit strapping information corresponding to the determined resistance.

Abstract: An electronic device includes a packaged device and a thermal dissipater. The packaged device includes a component that generates thermal energy, a package that encapsulates the component, and an interconnect that forms a portion of a high thermal conduction between the component and a circuit card. The thermal dissipater obtains the thermal energy using the circuit card and radiates the thermal energy.

Abstract: A computing device includes a module that connects to a main board and a short detector. The short detector applies a voltage to a first electrical contact of the module; while the voltage is applied: makes a comparison of a second voltage on a second electrical contact of the module to the voltage; makes a determination, based on the comparison, that the first electrical contact is connected to the second electrical contact via a short circuit; and in response to the determination, initiates remediation of the short circuit.

Abstract: An electronic device includes a packaged device and a thermal dissipater. The packaged device includes a component that generates thermal energy, a package that encapsulates the component, and an interconnect that forms a portion of a high thermal conduction between the component and a circuit card. The thermal dissipater obtains the thermal energy using the circuit card and radiates the thermal energy.

Abstract: A computing device includes a module that connects to a main board and a short detector. The short detector applies a voltage to a first electrical contact of the module; while the voltage is applied: makes a comparison of a second voltage on a second electrical contact of the module to the voltage; makes a determination, based on the comparison, that the first electrical contact is connected to the second electrical contact via a short circuit; and in response to the determination, initiates remediation of the short circuit.

Abstract: Memory short detection systems and methods include a power supply system with first power rail. A memory system includes a memory device connector that is configured to couple to a memory device and includes a first pin that is coupled to the first power rail and a second pin located adjacent the first pin. A short detection circuit is coupled to the first pin. The short detection circuit is configured to provide a first voltage from the first power rail, compare the first voltage to a first short detection voltage, and determine whether a short exists across the first pin and the second pin based on the comparing of the first voltage to the first short detection voltage. If a short is determined to exist across the first pin and the second pin, power is prevented from being provided to the memory device connector.

Abstract: Memory short detection systems and methods include a power supply system with first power rail. A memory system includes a memory device connector that is configured to couple to a memory device and includes a first pin that is coupled to the first power rail and a second pin located adjacent the first pin. A short detection circuit is coupled to the first pin. The short detection circuit is configured to provide a first voltage from the first power rail, compare the first voltage to a first short detection voltage, and determine whether a short exists across the first pin and the second pin based on the comparing of the first voltage to the first short detection voltage. If a short is determined to exist across the first pin and the second pin, power is prevented from being provided to the memory device connector.

Abstract: Memory short detection systems and methods include a power supply system with first power rail. A memory system includes a memory device connector that is configured to couple to a memory device and includes a first pin that is coupled to the first power rail and a second pin located adjacent the first pin. A short detection circuit is coupled to the first pin. The short detection circuit is configured to provide a first voltage from the first power rail, compare the first voltage to a first short detection voltage, and determine whether a short exists across the first pin and the second pin based on the comparing of the first voltage to the first short detection voltage. If a short is determined to exist across the first pin and the second pin, power is prevented from being provided to the memory device connector.

Abstract: A system and method of measuring real-time current is disclosed. The method includes calibrating a voltage measurement device. Calibrating includes measuring a real-time voltage difference between a first measurement node located proximate a first connector on a motherboard and a second measurement node located proximate a second connector on a power supply unit (PSU), the first and the second connectors coupled to provide power to the motherboard. Calibrating further includes averaging the real-time voltage difference for a plurality of measurements; computing a resistance of the coupling based at least on a long-duration averaged current from the PSU and the averaged real-time voltage difference, the resistance varying over time; and reporting the resistance of the coupling to the voltage measurement device. The method also includes measuring a real-time current of the PSU at the voltage measurement device based at least on the resistance of the coupling and the real-time voltage difference.

Abstract: A system and method of measuring real-time current is disclosed. The method includes calibrating a voltage measurement device. Calibrating includes measuring a real-time voltage difference between a first measurement node located proximate a first connector on a motherboard and a second measurement node located proximate a second connector on a power supply unit (PSU), the first and the second connectors coupled to provide power to the motherboard. Calibrating further includes averaging the real-time voltage difference for a plurality of measurements; computing a resistance of the coupling based at least on a long-duration averaged current from the PSU and the averaged real-time voltage difference, the resistance varying over time; and reporting the resistance of the coupling to the voltage measurement device. The method also includes measuring a real-time current of the PSU at the voltage measurement device based at least on the resistance of the coupling and the real-time voltage difference.

Abstract: A system and method of measuring real-time current is disclosed. The method includes calibrating a voltage measurement device. Calibrating includes measuring a real-time voltage difference between a first measurement node located proximate a first connector on a motherboard and a second measurement node located proximate a second connector on a power supply unit (PSU), the first and the second connectors coupled to provide power to the motherboard. Calibrating further includes averaging the real-time voltage difference for a plurality of measurements; computing a resistance of the coupling based at least on a long-duration averaged current from the PSU and the averaged real-time voltage difference, the resistance varying over time; and reporting the resistance of the coupling to the voltage measurement device. The method also includes measuring a real-time current of the PSU at the voltage measurement device based at least on the resistance of the coupling and the real-time voltage difference.

Abstract: Memory short detection systems and methods include a power supply system with first power rail. A memory system includes a memory device connector that is configured to couple to a memory device and includes a first pin that is coupled to the first power rail and a second pin located adjacent the first pin. A short detection circuit is coupled to the first pin. The short detection circuit is configured to provide a first voltage from the first power rail, compare the first voltage to a first short detection voltage, and determine whether a short exists across the first pin and the second pin based on the comparing of the first voltage to the first short detection voltage. If a short is determined to exist across the first pin and the second pin, power is prevented from being provided to the memory device connector.

Abstract: A system and method of measuring real-time current is disclosed. The method includes calibrating a voltage measurement device. Calibrating includes measuring a real-time voltage difference between a first measurement node located proximate a first connector on a motherboard and a second measurement node located proximate a second connector on a power supply unit (PSU), the first and the second connectors coupled to provide power to the motherboard. Calibrating further includes averaging the real-time voltage difference for a plurality of measurements; computing a resistance of the coupling based at least on a long-duration averaged current from the PSU and the averaged real-time voltage difference, the resistance varying over time; and reporting the resistance of the coupling to the voltage measurement device. The method also includes measuring a real-time current of the PSU at the voltage measurement device based at least on the resistance of the coupling and the real-time voltage difference.

Abstract: A redundant clock system for use in a computer is provided including a first oscillator which produces first reference clock signals; a second oscillator which produces second reference clock signals; a third oscillator which produces third reference clock signals; a first multiplexer which receives the first, second and third reference clock signals from the first, second and third oscillators and which provides a designated one of the received reference clock signals as a selected reference clock signal; a second multiplexer which receives the first, second and third reference clock signals from the first, second and third oscillators and which provides a designated one of the received reference clock signals as a selected reference clock signal; a third multiplexer which receives the first, second and third reference clock signals from the first, second and third oscillators and which provides a designated one of the received reference clock signals as a selected reference clock signal; a first phase-locke