Patents by Inventor James Lawrence GORECKI
James Lawrence GORECKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10110204Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.Type: GrantFiled: March 31, 2017Date of Patent: October 23, 2018Assignee: INPHI CORPORATIONInventors: James Lawrence Gorecki, Han-Yuan Tan
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Patent number: 10103717Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.Type: GrantFiled: November 1, 2017Date of Patent: October 16, 2018Assignee: INPHI CORPORATIONInventors: James Lawrence Gorecki, Han-Yuan Tan
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Patent number: 9921593Abstract: The present disclosure provides a detailed description of techniques for implementing a wideband low dropout voltage regulator with power supply rejection boost. More specifically, some embodiments of the present disclosure are directed to a voltage regulator comprising a voltage regulator core powered by a supply voltage and providing a regulated voltage output, and a power supply feed forward injection module delivering an injection signal to the voltage regulator core to effect a power supply rejection of the supply voltage variation from the regulated voltage. In one or more embodiments, the injection signal is determined from the supply voltage variation and a gain factor that is based on various design attributes of the output stage of the voltage regulator core. In one or more embodiments, the power supply feed forward injection module comprises a supply voltage sense circuit, a low pass filter, and one or more selectable transconductance amplifiers.Type: GrantFiled: December 9, 2016Date of Patent: March 20, 2018Assignee: INPHI CORPORATIONInventors: James Lawrence Gorecki, Han-Yuan Tan
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Publication number: 20180054191Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.Type: ApplicationFiled: November 1, 2017Publication date: February 22, 2018Inventors: James Lawrence GORECKI, Han-Yuan TAN
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Patent number: 9837998Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.Type: GrantFiled: December 9, 2016Date of Patent: December 5, 2017Assignee: INPHI CORPORATIONInventors: James Lawrence Gorecki, Han-Yuan Tan
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Patent number: 9716480Abstract: This disclosure relates to the field of amplifiers for multi-level optical communication and more particularly to techniques for trans-impedance amplifiers (TIA) with gain control. The claimed embodiments address the problem of implementing a low cost TIA that exhibits high linearity, low noise, low power, and wide bandwidth. More specifically, some claims are directed to approaches for providing TIA gain control using a plurality of inverter-based replica gain control cells controlled by a feedback loop to manage the current into the amplifying output stage and thereby the TIA output voltage.Type: GrantFiled: September 19, 2016Date of Patent: July 25, 2017Assignee: INPHI CORPORATIONInventors: James Lawrence Gorecki, Irene Quek
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Publication number: 20170207864Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.Type: ApplicationFiled: March 31, 2017Publication date: July 20, 2017Inventors: James Lawrence GORECKI, Han-Yuan TAN
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Patent number: 9647643Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.Type: GrantFiled: August 8, 2016Date of Patent: May 9, 2017Assignee: INPHI CORPORATIONInventors: James Lawrence Gorecki, Han-Yuan Tan
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Publication number: 20170126329Abstract: The present disclosure provides a detailed description of techniques for implementing a wideband low dropout voltage regulator with power supply rejection boost. More specifically, some embodiments of the present disclosure are directed to a voltage regulator comprising a voltage regulator core powered by a supply voltage and providing a regulated voltage output, and a power supply feed forward injection module delivering an injection signal to the voltage regulator core to effect a power supply rejection of the supply voltage variation from the regulated voltage. In one or more embodiments, the injection signal is determined from the supply voltage variation and a gain factor that is based on various design attributes of the output stage of the voltage regulator core. In one or more embodiments, the power supply feed forward injection module comprises a supply voltage sense circuit, a low pass filter, and one or more selectable transconductance amplifiers.Type: ApplicationFiled: December 9, 2016Publication date: May 4, 2017Inventors: James Lawrence GORECKI, Han-Yuan TAN
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Publication number: 20170126217Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.Type: ApplicationFiled: December 9, 2016Publication date: May 4, 2017Inventors: James Lawrence GORECKI, Han-Yuan TAN
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Patent number: 9552006Abstract: The present disclosure provides a detailed description of techniques for implementing a wideband low dropout voltage regulator with power supply rejection boost. More specifically, some embodiments of the present disclosure are directed to a voltage regulator comprising a voltage regulator core powered by a supply voltage and providing a regulated voltage output, and a power supply feed forward injection module delivering an injection signal to the voltage regulator core to effect a power supply rejection of the supply voltage variation from the regulated voltage. In one or more embodiments, the injection signal is determined from the supply voltage variation and a gain factor that is based on various design attributes of the output stage of the voltage regulator core. In one or more embodiments, the power supply feed forward injection module comprises a supply voltage sense circuit, a low pass filter, and one or more selectable transconductance amplifiers.Type: GrantFiled: March 9, 2015Date of Patent: January 24, 2017Assignee: INPHI CORPORATIONInventors: James Lawrence Gorecki, Han-Yuan Tan
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Patent number: 9553569Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.Type: GrantFiled: February 4, 2015Date of Patent: January 24, 2017Assignee: INPHI CORPORATIONInventors: James Lawrence Gorecki, Han-Yuan Tan
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Publication number: 20170005633Abstract: This disclosure relates to the field of amplifiers for multi-level optical communication and more particularly to techniques for trans-impedance amplifiers (TIA) with gain control. The claimed embodiments address the problem of implementing a low cost TIA that exhibits high linearity, low noise, low power, and wide bandwidth. More specifically, some claims are directed to approaches for providing TIA gain control using a plurality of inverter-based replica gain control cells controlled by a feedback loop to manage the current into the amplifying output stage and thereby the TIA output voltage.Type: ApplicationFiled: September 19, 2016Publication date: January 5, 2017Inventors: James Lawrence GORECKI, Irene QUEK
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Publication number: 20160352372Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.Type: ApplicationFiled: August 8, 2016Publication date: December 1, 2016Inventors: James Lawrence GORECKI, Han-Yuan TAN
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Patent number: 9473090Abstract: This disclosure relates to the field of amplifiers for multi-level optical communication and more particularly to techniques for trans-impedance amplifiers (TIA) with gain control. The claimed embodiments address the problem of implementing a low cost TIA that exhibits high linearity, low noise, low power, and wide bandwidth. More specifically, some claims are directed to approaches for providing TIA gain control using a plurality of inverter-based replica gain control cells controlled by a feedback loop to manage the current into the amplifying output stage and thereby the TIA output voltage.Type: GrantFiled: November 21, 2014Date of Patent: October 18, 2016Assignee: INPHI CORPORATIONInventors: James Lawrence Gorecki, Irene Quek
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Patent number: 9432000Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.Type: GrantFiled: February 4, 2015Date of Patent: August 30, 2016Assignee: INPHI CORPORATIONInventors: James Lawrence Gorecki, Han-Yuan Tan
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Publication number: 20160149548Abstract: This disclosure relates to the field of amplifiers for multi-level optical communication and more particularly to techniques for trans-impedance amplifiers (TIA) with gain control. The claimed embodiments address the problem of implementing a low cost TIA that exhibits high linearity, low noise, low power, and wide bandwidth. More specifically, some claims are directed to approaches for providing TIA gain control using a plurality of inverter-based replica gain control cells controlled by a feedback loop to manage the current into the amplifying output stage and thereby the TIA output voltage.Type: ApplicationFiled: November 21, 2014Publication date: May 26, 2016Inventors: James Lawrence GORECKI, Irene QUEK