Abstract: A switch signal generator circuit that may form part of a digital to analog converter is provided. The switch signal generator circuit may include a first switch that controls a high reference gate voltage. The high reference gate voltage may provide the ON state voltage for a plurality of switches that control the coupling of a high reference voltage to the digital to analog converter. The switch signal generator circuit may include a second switch that controls a low reference gate voltage. The low reference gate voltage may provide the ON state voltage for a plurality of switches that control the coupling of a low reference voltage to the digital to analog converter. The switch signal generator circuit may also include a resistor. In one embodiment of the invention, a current conducted by the first switch and/or a current conducted by the second switch may each be proportional to a current conducted by the resistor. One of the switches in the switch generator circuit may be a P channel switch.

Abstract: A trimdac circuit for adjusting the output of a digital-to-analog converter (DAC) is provided. The trimdac may be used to adjust a plurality of resistor segments in the DAC. The trimdac may include a programmable Read Only Memory (ROM) or other suitable memory device. The ROM may include a plurality of multi-bit digital words. Each of the multi-bit digital words may control a plurality, and most preferably a pair of variable resistance circuits. Each of the pair of variable resistance circuits may adjust a resistor segment of the DAC.

Abstract: Digital to analog converter circuits and methods are provided for producing an analog output voltage indicative of a digital input signal with at least partial insensitivity to error gradients. Described are split-core resistive elements, which include a plurality of one-dimensional or multi-dimensional resistive strings, that may be used to reduce or substantially eliminate the effects that error gradients have on the linearity of the analog output voltages of a resistive string or interpolating amplifier DACs. The resistor strings that make up the split-core resistive elements are configured in such a manner that combining respective output voltages from each of the resistor strings results in an analog output voltage that is at least partially insensitive to the effects of error gradients.

Abstract: A trimdac circuit for adjusting the output of a digital-to-analog converter (DAC) is provided. The trimdac may be used, to adjust a plurality of resistor segments in the DAC. The trimdac may include a programmable Read Only Memory (ROM) or other suitable memory device. The ROM may include a plurality of multi-bit digital words. Each of the multi-bit digital words may control a plurality, and most preferably a pair of variable resistance circuits.

Abstract: A digital to analog converter that receives a digital signal and that converts the digital signal to an analog input signal is provided. The converter may include a group of most significant bits. The group is decoded to drive a plurality of equivalent most significant segments. The converter may also include a second group of bits. The second group is decoded to drive a second plurality of equivalent segments.

Abstract: A voltage interpolation circuit for a digital-to-analog converter comprises a differential amplifier with composite input devices, each of which is composed of multiple active subtransistors. Interpolation is effected between a first voltage and a second voltage by selectively connecting the gates of the active subtransistors in one of the composite devices to either the first voltage or the second voltage. Each active subtransistor operates in conjunction with a voltage-controlled degeneration subtransistor to form a functional subtransistor pair. Using the nonlinear conductance characteristic of MOS devices operated in the triode region, the transconductance of each functional subtransistor pair is modulated in such a way as to be made relatively insensitive to changes in effective gate-to-source voltage V.sub.GS ', so that the interpolation circuit produces equally sized interpolated voltage steps at an analog output.