Abstract: A method of merging a first data stream with a second data stream to generate a third data stream. The method comprises receiving a first packet from the first data stream, the first packet containing a first packet ID and a first data payload and receiving a second packet from the second data stream, the second packet containing a second packet ID and a second data payload. The method also includes storing first data in a plurality of packet ID arrival registers, a first portion of the first data indicating that the first packet ID is equal to the ID associated with a first of the plurality of the packet ID arrival registers and storing second data in the plurality of packet ID arrival registers, a first portion of the second data indicating that the second packet ID is equal to the ID associated with the second of the plurality of the packet ID arrival registers.

Abstract: A method performed by a computer system that includes a host processor coupled to a first bus, a first switch coupled to the first bus and a second bus, a second switch coupled to the second bus and a third bus, and a device coupled to the third bus. The method of storing information in a configuration register in the device includes: issuing a first configuration transaction onto the first bus; forwarding the first configuration transaction to the second bus; translating the first configuration transaction into a second configuration transaction; forwarding the second configuration transaction to the third bus; and storing information in the configuration register.

Abstract: A method performed by a computer system that includes a host processor coupled to a first bus, a first switch coupled to the first bus and a second bus, a second switch coupled to the second bus and a third bus, and a device coupled to the third bus. The method of storing information in a configuration register in the device includes: issuing a first configuration transaction onto the first bus; forwarding the first configuration transaction to the second bus; translating the first configuration transaction into a second configuration transaction; forwarding the second configuration transaction to the third bus; and storing information in the configuration register.

Abstract: Speculative prefetching during DMA reads in a message-passing, queue-oriented bus system is controlled by creating a special data structure, called a “DMA scoreboard”, for each work queue entry associated with a DMA read. The DMA scoreboard tracks the completion of DMA writes and reads by monitoring acknowledgements received from DMA writes and data tags received from DMA read responses. The DMA scoreboard also contains a section that indicates the current PCI address, and size and number of prefetches to be performed. After a DMA read has completed, the PCI current address is incremented to obtain a new PCI address for the first prefetch request. A new work queue entry is then created from the information in the DMA scoreboard to perform the prefetch.

Abstract: PCI load/store operations and DMA operations are implemented via work queue pairs in a message-passing, queue-oriented bus architecture. PCI address space is divided into segments and, each segment, in turn, is divided into regions. A separate work queue is assigned to each segment. A first portion of a PCI address is matched against the address ranges represented by the segments and used to select a memory segment and its corresponding work queue. An entry in the work queue holds a second portion of the PCI address which specifies a region within the selected segment that is assigned to a specific PCI device. In one embodiment, PIO load/store operations are implemented by selecting a work queue assigned to PIO operations and creating a work queue entry with the PCI address of a register on a PCI device and a pointer to the PIO data. The work queue entry is sent to a PCI bridge where the PCI address is extracted and used to program the appropriate device register with the data using the data pointer.

Abstract: An I/O device that includes: an input port; an input buffer coupled to the input port; an internal port operable to store packets generated by the I/O device; an internal buffer coupled to the internal port; a plurality of packet ID arrival registers coupled to the input port and the internal port; autocorrelation logic coupled to the plurality of packet ID arrival registers; an arbiter coupled to the autocorrelation logic; a packet selector coupled to the arbiter, the input buffer and the internal buffer; and an output port coupled to the packet selector.

Abstract: Speculative prefetching during DMA reads in a message-passing, queue-oriented bus system is controlled by creating a special data structure, called a “DMA scoreboard”, for each work queue entry associated with a DMA read. The DMA scoreboard tracks the completion of DMA writes and reads by monitoring acknowledgements received from DMA writes and data tags received from DMA read responses. The DMA scoreboard also contains a section that indicates the current PCI address, and size and number of prefetches to be performed. After a DMA read has completed, the PCI current address is incremented to obtain a new PCI address for the first prefetch request. A new work queue entry is then created from the information in the DMA scoreboard to perform the prefetch.

Abstract: In a message-passing, queue-oriented bus system, a separate interrupt work queue assigned to each interrupt line for each PCI device sends interrupt information packets from the device to the host. To prevent an interrupt from being transmitted before another DMA data write has been completed, interrupt requests are held on the interrupt work queue until all outstanding data transfer requests have been acknowledged. A special data structure called an interrupt scoreboard is created for each interrupt work queue entry associated with a DMA write in order to track the DMA data transfer. When an interrupt is received, the interrupt scoreboard acquires a “snapshot” of the state of the pending data requests and tracks the pending DMA transfers. When acknowledgement messages have been received for all pending DMA transfer requests, then the interrupt data packet is transmitted so that the interrupt can be serviced.

Abstract: Speculative prefetching during DMA reads in a message-passing, queue-oriented bus system is controlled by creating a special data structure, called a “DMA scoreboard”, for each work queue entry associated with a DMA read. The DMA scoreboard tracks the completion of DMA writes and reads by monitoring acknowledgements received from DMA writes and data tags received from DMA read responses. The DMA scoreboard also contains a section that indicates the current PCI address, and size and number of prefetches to be performed. After a DMA read has completed, the PCI current address is incremented to obtain a new PCI address for the first prefetch request. A new work queue entry is then created from the information in the DMA scoreboard to perform the prefetch.

Abstract: An I/O device that includes: an input port; an input buffer coupled to the input port; an internal port operable to store packets generated by the I/O device; an internal buffer coupled to the internal port; a plurality of packet ID arrival registers coupled to the input port and the internal port; autocorrelation logic coupled to the plurality of packet ID arrival registers; an arbiter coupled to the autocorrelation logic; a packet selector coupled to the arbiter, the input buffer and the internal buffer; and an output port coupled to the packet selector.

Abstract: A method of merging a first data stream with a second data stream to generate a third data stream. The method comprises receiving a first packet from the first data stream, the first packet containing a first packet ID and a first data payload and receiving a second packet from the second data stream, the second packet containing a second packet ID and a second data payload. The method also includes storing first data in a plurality of packet ID arrival registers, a first portion of the first data indicating that the first packet ID is equal to the ID associated with a first of the plurality of the packet ID arrival registers and storing second data in the plurality of packet ID arrival registers, a first portion of the second data indicating that the second packet ID is equal to the ID associated with the second of the plurality of the packet ID arrival registers.

Abstract: A method and apparatus for producing an electronic circuit which allows a device to be connected to a bus, such as a system bus in a computer. The invention accepts user specified parameters for configuring a device adapter which interfaces the device to the bus, and thereafter generates a customized device adapter based on such user specified parameters. By using a common design macro, which is programmable, a user can easily specify and generate custom device adapters for a plurality of dissimilar devices to be connected to the bus. A resulting adapter architecture allows for multiple, dissimilar devices to interface to a computer bus with a single device adapter integrated circuit or card.

Abstract: A method and apparatus for producing an electronic circuit which allows a device to be connected to a bus, such as a system bus in a computer. The invention accepts user specified parameters for configuring a device adapter which interfaces the device to the bus, and thereafter generates a customized device adapter based on such user specified parameters. By using a common design macro, which is programmable, a user can easily specify and generate custom device adapters for a plurality of dissimilar devices to be connected to the bus. A resulting adapter architecture allows for multiple, dissimilar devices to interface to a computer bus with a single device adapter integrated circuit or card.

Abstract: A system for converting known speech segments into machine storable binary signals for the purpose of later attempting a match between a stored signal and an incoming signal using autocorrelation techniques. Through the use of a clipper and a sample and hold register, the system converts an incoming speech signal into a bit stream signal. Two successive groups of bits called frames are stored in separate registers. A bit-by-bit correlation is performed on the bits stored in the separate registers and a counter is indexed as a function of the correlation. A memory is provided for maintaining a record of the counts associated with each speech segment for later attempting computer pattern matching against received unknown speech segments.

Abstract: A portable transaction processing calculator has a keyboard and a display window along with slots for holding at least a pair of credit cards. One of the cards includes storage means therein and is electrically connected with the calculator, and another card has optical or other readable data thereon and readable by optical or other equipment. A selector switch on the calculator selects one of four different operations.

Abstract: A method and implementation apparatus for converting analog signals, such as speech signals, into digital data signals, with improved fidelity by the use of dithering techniques coupled with amplitude clipping and filtering operations.

Abstract: The present invention relates to a speech recognition system and the method therefor, which analyzes a sampled clipped speech signal for identifying a spoken utterance. An input signal representative of the spoken utterance is passed through a clipper to generate a clipped input signal. A sampler generates a plurality of discrete binary values, each discrete binary value corresponding to a sample value of the clipped input signal. A processor then analyzes the plurality of sample values thereby identifying the spoken utterance. Analysis includes determining linear prediction coefficients of the autocorrelation function of speech utterences.