Abstract: A method of testing error correction/detection logic may involve providing each of a set of n data bit combinations to the error correction/detection logic. Each data bit combination has n bits, and the n data bit combinations may be created by creating an initial data bit combination whose data bits have the same logical value and then shifting a bit having the opposite value across the initial data bit combination. In response to being provided with the n data bit combinations, the error correction/detection logic generates a set of check bits for each of the n data bit combinations. The set of check bits generated by the error correction/detection logic for each of the n data bit combinations may then be verified.

Abstract: Commands requesting access to a storage medium may be reordered by locating an insertion point for a new command in a first list of commands in a command queue and checking at least one of the following conditions: that the end of the command queue is within a first number of queue elements from the first insertion point; and/or that inserting the new command at the insertion point would not cause the first list to exceed a maximum list size. If the condition(s) are met, the new command may be inserted at the insertion point; otherwise, another insertion point may be selected. Thus, insertion points may be restricted to those that occur within a first number of queue elements from the end of the queue and/or to those that do not cause any lists within the command queue to exceed a certain size.

Abstract: A method of testing error correction/detection logic may involve providing each of a set of n data bit combinations to the error correction/detection logic. Each data bit combination has n bits, and the n data bit combinations may be created by creating an initial data bit combination whose data bits have the same logical value and then shifting a bit having the opposite value across the initial data bit combination. In response to being provided with the n data bit combinations, the error correction/detection logic generates a set of check bits for each of the n data bit combinations. The set of check bits generated by the error correction/detection logic for each of the n data bit combinations may then be verified.