Abstract: The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.

Abstract: Machine-readable media, methods, and apparatus are described to issue transactions to a memory. In some embodiments, a memory controller may select pending transactions based upon selection criteria and may issue the selected transactions to memory. Further, the memory controller may close a page of the memory accessed by a write transaction in response to determining that the write transaction is the last write transaction of a series of one or more write transactions.

Abstract: Methods and apparatuses for improving processor performance in a multi-processor system by optimizing accesses to memory. Processors can track the state of a memory such that the memory can be efficiently utilized in a multi-processor system including the ability to decode incoming snoop addresses from other processors, comparing them to contents of a memory tracking register(s), and updating tracking register(s) appropriately. Likewise, the transactions from other non-processor bus agents and/or bus mastering devices, such as a bus bridge, memory controller, Input/output (I/O), and graphics could also be tracked.

Abstract: Machine-readable media, methods, and apparatus are described which process memory transactions. In some embodiments, a processor requests an external memory controller to close a storage location of a memory associated with a first memory transaction based upon a relationship between the first memory transaction and a second memory transaction.

Abstract: Machine-readable media, methods, and apparatus are described which order memory transactions to increase utilization of multiple memory channels. In some embodiments, a processor may determine an issue order for memory transactions based on the memory channels that are to service the memory transactions. In some embodiments, the processor attempts to obtain an issue order that minimizes or reduces the number of idle periods experienced by the memory channels. Further, the processor may issue the memory transactions to an external memory controller for servicing in the determined issue order.

Abstract: Machine-readable media, methods, and apparatus are described which process memory transactions. In some embodiments, a memory controller of a processor and/or chipset may adaptively determine whether to close pages of a memory in an attempt to increase perceived memory performance.

Abstract: Methods and apparatus for a memory system using a new memory module architecture are disclosed. In one embodiment, the memory module has two ranks of memory devices, each rank connected to a corresponding one of two 64-bit-wide data registers. The data registers connect to two 64-bit-wide ports of a 128:64 multiplexer/demultiplexer, and a 64-bit-wide data buffer connects to the opposite port of the multiplexer/demultiplexer. A controller synchronizes the operation of the data registers, the multiplexer/demultiplexer, and the data buffer. In an operating environment, the data buffer connects to a memory bus. When a data access is performed, both ranks exchange data signaling with their corresponding data registers during a single data access. At the buffer, the memory bus data transfer occurs in two consecutive clock cycles, one cycle for each rank. This allows the memory bus transfer rate to double for the same memory bus width and memory device speed.

Abstract: A method of controlling power states in a memory device includes determining if a power-down command is received. A first lower power state is entered if the power-down command is received and the memory device is in a first state. A second lower power state is entered if the power-down command is received and if the memory device is in a second state. The second lower power state is lower than the first lower power state. The memory device remains in a normal operation power state if the power-down command is not received.

Abstract: Methods and apparatus for a memory system using line termination circuits in each memory unit (e.g., integrated circuit memory device) are disclosed. The memory unit contains termination control logic that sets the state of a controllable termination circuit to control reflections on the data bus. The termination control logic determines the proper state for the termination circuit from the state of its memory unit, and in some cases, from the approximate state of the data bus as gleaned from commands decoded from the command/address bus. A termination configuration register on the unit can be used to define the appropriate termination state for each unit state and/or data bus state.

Abstract: A memory controller or other device may be programmed with a data mask mapping scheme. A selection device within the memory controller may be set with the data mask mapping scheme between data and a data mask. In one embodiment, a storage device may be included and programmed with the data mask mapping scheme.

Abstract: A data mask map may be programmed into a storage device in various ways. In one embodiment, the data mask is hardwired into a selection device to reorder either the data mask bits or the data chunks. In another embodiment, a data mask map is retrieved from a location in memory. In still another embodiment, the data mask map is determined through an algorithm.

Abstract: The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.

Abstract: A method of handling memory read return data from different time domains includes determining a number of distinct memory device ranks. A time domain for each of the distinct memory device ranks is determined. A transaction is scheduled based on the time domain for each of the distinct memory device ranks so that at least one of data collisions and out-of-order data returns are prevented.

Abstract: A data mask map may be programmed into a storage device in various ways. In one embodiment, the data mask is hardwired into a selection device to reorder either the data mask bits or the data chunks. In another embodiment, a data mask map is retrieved from a location in memory. In still another embodiment, the data mask map is determined through an algorithm.

Abstract: Machine-readable media, methods, and apparatus are described which process memory transactions. In some embodiments, a processor or other external components provide a memory controller with decoded memory addresses. The memory controller then may access the memory with the processor decoded address without decoding the address itself. In other embodiments, a processor or other external components provide a memory controller with partially decoded memory addresses. The memory controller then generates a decoded address from the partially decoded address and may access the memory with the generated decoded address.

Abstract: A system and method for controlling the direction of data flow in a memory system is provided. The system comprising memory devices, a memory controller, a buffering structure, and a data flow director. The memory controller sends data, such as read-data, write-data, address information and command information, to the memory devices and receives data from the memory devices. The buffering structure interconnects the memory device and the memory controller. The buffering structure is adapted to operate in a bi-directional manner for the direction of data flow therethrough. The data flow director, which may reside in the buffering structure, the memory controller, the memory devices, or an external device, controls the direction of data flow through the buffering structure based on the data transmitted from the memory controller or the memory device.

Abstract: A flowchart and circuit for tracking memory page accesses in a multi-processor computing system to optimize memory bandwidth utilization.

Abstract: A data mask map may be programmed into a storage device in various ways. In one embodiment, the data mask is hardwired into a selection device to reorder either the data mask bits or the data chunks. In another embodiment, a data mask map is retrieved from a location in memory. In still another embodiment, the data mask map is determined through an algorithm.

Abstract: In some embodiments, the invention includes a system having a memory controller, a bus, and first and second memory devices. The memory controller requests read and write operations and operates with a burst length. The first and second memory devices are coupled to the memory controller through the bus, the first and second memory devices each having a prefetch length that is greater than the burst length, but performing the requested read and write operations with the burst length. Other embodiments are described and claimed.

Abstract: A data mask map may be programmed into a storage device in various ways. In one embodiment, the data mask is hardwired into a selection device to reorder either the data mask bits or the data chunks. In another embodiment, a data mask map is retrieved from a location in memory. In still another embodiment, the data mask map is determined through an algorithm.