Patents by Inventor James M. Harper
James M. Harper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8125082Abstract: A method that solves the increased nucleation temperature that is exhibited during the formation of cobalt disilicides in the presence of Ge atoms is provided. The reduction in silicide formation temperature is achieved by first providing a structure including a Co layer including at least Ni, as an additive element, on top of a SiGe containing substrate. Next, the structure is subjected to a self-aligned silicide process which includes a first anneal, a selective etching step and a second anneal to form a solid solution of (Co, Ni) disilicide on the SiGe containing substrate. The Co layer including at least Ni can comprise an alloy layer of Co and Ni, a stack of Ni/Co or a stack of Co/Ni. A semiconductor structure including the solid solution of (Co, Ni) disilicide on the SiGe containing substrate is also provided.Type: GrantFiled: May 15, 2008Date of Patent: February 28, 2012Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Roy A. Carruthers, Jia Chen, Christopher Detavernier, James M. Harper, Christian Lavoie
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Publication number: 20080246120Abstract: A method that solves the increased nucleation temperature that is exhibited during the formation of cobalt disilicides in the presence of Ge atoms is provided. The reduction in silicide formation temperature is achieved by first providing a structure including a Co layer including at least Ni, as an additive element, on top of a SiGe containing substrate. Next, the structure is subjected to a self-aligned silicide process which includes a first anneal, a selective etching step and a second anneal to form a solid solution of (Co, Ni) disilicide on the SiGe containing substrate. The Co layer including at least Ni can comprise an alloy layer of Co and Ni, a stack of Ni/Co or a stack of Co/Ni. A semiconductor structure including the solid solution of (Co, Ni) disilicide on the SiGe containing substrate is also provided.Type: ApplicationFiled: May 15, 2008Publication date: October 9, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, Roy A. Carruthers, Jia Chen, Christophe Detavernier, James M. Harper, Christian Lavoie
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Patent number: 7384868Abstract: A method that solves the increased nucleation temperature that is exhibited during the formation of cobalt disilicides in the presence of Ge atoms is provided. The reduction in silicide formation temperature is achieved by first providing a structure including a Co layer including at least Ni, as an additive element, on top of a SiGe containing substrate. Next, the structure is subjected to a self-aligned silicide process which includes a first anneal, a selective etching step and a second anneal to form a solid solution of (Co, Ni) disilicide on the SiGe containing substrate. The Co layer including at least Ni can comprise an alloy layer of Co and Ni, a stack of Ni/Co or a stack of Co/Ni. A semiconductor structure including the solid solution of (Co, Ni) disilicide on the SiGe containing substrate is also provided.Type: GrantFiled: September 15, 2003Date of Patent: June 10, 2008Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Roy A. Carruthers, Jia Chen, Christophe Detavernier, James M. Harper, Christian Lavoie
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Patent number: 6444578Abstract: The present invention relates to a method of reducing Si consumption during a self-aligned silicide process which employs a M—Si or M—Si—Ge alloy, where M is Co, Ni or CoNi and a blanket layer of Si. The present invention is particularly useful in minimizing Si consumption in shallow junction and thin silicon-on-insulator (SOI) electronic devices.Type: GrantFiled: February 21, 2001Date of Patent: September 3, 2002Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Roy Arthur Carruthers, Kevin K. Chan, Guy M. Cohen, Kathryn Wilder Guarini, James M. Harper, Christian Lavoie, Paul M. Solomon
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Patent number: 5832507Abstract: A method and apparatus for converting ASCII path names to parsed path name structures provides downward compatibility so that program modules written for modern operating systems which provide parsed path name structure inputs may be run under older operating systems which provide ASCII path name inputs. The method includes, in its most basic form, the steps of converting the prefix and file name of an ASCII path name to a unicode string, then converting the unicode string to a parsed path structure. In a preferred embodiment of the invention, the method is implemented in compiled object code written in the "C" computer programming language.Type: GrantFiled: April 1, 1996Date of Patent: November 3, 1998Assignee: Sun Microsystems, Inc.Inventors: James M. Harper, Brian Berliner
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Patent number: 5771385Abstract: In a computing system, debug flags for software development, testing, and debugging of a module of the operating system are retrieved and set. The module under development is provided with a debugging message handler and a lookup table of debugging flags. The table maps the debugging flags to memory locations containing the present state of the flags. A debugging message is generated at the application-level by a user desiring to monitor or alter the state of the debugging flags. The debugging message handler decodes the debugging message using the table, and the module reports or alters the debugging flag accordingly. In this manner, real-time program evaluation and control can be achieved without the conventional debugging software packages.Type: GrantFiled: March 29, 1996Date of Patent: June 23, 1998Assignee: Sun Microsystems, Inc.Inventor: James M. Harper
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Patent number: 5701474Abstract: Handle-based finding operations for search operations in an operating system in a computing system are converted into non-handle-based finding operations. The invention is responsive to a program module performing search operations specifying a file search path and has a find first module, a find next module and a find close module. The find first module, in response to a find first call from the program module, locates a search block for use in storing file identification information for a first file in the file search path. The find first module marks the search block as "in use," generates a handle identifying the search block and passes the handle back to the program module. The find next module is responsive to a find next call containing the handle. The find next module converts the handle into a search block address and locates the search block from the search block address. The search block is used to store the file identification information for a next file in the file search path.Type: GrantFiled: March 29, 1996Date of Patent: December 23, 1997Assignee: Sun Microsystems, Inc.Inventor: James M. Harper
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Patent number: 5401677Abstract: An improved process for the formation of high quality, high yield platinum silicides on silicon wafers uses a post sputter platinum deposition and high vacuum bake to complete the first step of silicide reaction, resulting in Pt.sub.2 Si formation before sinter. This additional process step is then followed by a 500.degree. to 900.degree. C. sinter. The use of a high vacuum bake provides easy control of O.sub.2 and H.sub.2 O impurities. The vacuum bake can be done in any high vacuum tool. The bake temperatures range from 200.degree. to 450.degree. C. at 5.times.10.sup.-6 torr, with an in-situ bake time of 3 to 5 minutes or an ex-situ bake time of 10 to 30 minutes, depending on batch size or tool. A particular advantage of the process is that it can be performed in existing tools.Type: GrantFiled: December 23, 1993Date of Patent: March 28, 1995Assignee: International Business Machines CorporationInventors: Robert D. Bailey, Cyril Cabral, Jr., Brian Cunningham, Hormazdyar M. Dalal, James M. Harper, Viraj Sardesai, Horatio S. Wildman, Thomas O. Williams
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Patent number: 4250009Abstract: An energetic particle beam is accelerated towards a sputtering target. The target is located at an angle to the path of the beam (although it need not be). The target material which is dislodged by the ion beam can be directed towards a substrate. The material is composed of atoms forming both positive and negative ions. The voltage difference between the target and the substrate can be adjusted to be positive or negative so that either positive ions or negative ions can be accelerated to the substrate by means of adjusting the target-substrate voltage difference. In addition, means can be provided for collecting electrons included with the ions moving towards and away from the target. Such means can comprise a grid located adjacent to the target. It is also possible that electrons can be collected by means of an electric field confining structure which permits the ions to pass through while the electrons are deflected. Techniques.Type: GrantFiled: May 18, 1979Date of Patent: February 10, 1981Assignee: International Business Machines CorporationInventors: Jerome J. Cuomo, Richard J. Gambino, James M. Harper, John D. Kupstis