Abstract: An apparatus for accelerating the speed of memory access cycles in a multi-bank memory. The apparatus includes decode logic that pre-decodes bank information from a requested address signal while the corresponding request is queued in the request queue. The pre-decode logic is propagated to the memory controller, preferably by re-insertion into the request queue, to facilitate more rapid memory accesses.

Abstract: A present request includes a present bank select that maps the present request to one bank of a memory having multiple banks. A first request includes a first bank select that maps the first request to one bank of the memory, and a second request includes a second bank select that maps the second request to one bank of the memory. A method of arbitrating requests to the memory includes the steps of (a) processing a present request to access the memory; (b) receiving a first request to access the memory and a second request to access the memory; (c) selecting from the first request and the second request, a next request to access the memory; and (d) processing the next request to access the memory. Furthermore, the selecting step of the method is dependent upon the present bank select, the first bank select, and the second bank select. A memory controller and a computer system which implement the method of arbitrating requests is also disclosed.

Abstract: Multiple subsystem I/O (Input/Output) buses are coupled to one or more system buses of a computer system by interface circuits which perform necessary decoding of memory space and I/O (Input/Output) space for allocation of portions of the memory space and the I/O (Input/Output) space to each I/O (Input/Output) bus. The interface circuits also translate fixed addresses within each I/O (Input/Output) bus to permit proper operation of the I/O (Input/Output) buses with the computer system. The interface circuits are programmed by the computer system to define the allocated memory spaces and I/O (Input/Output) spaces for the corresponding I/O (Input/Output) buses. Programming of the I/O (Input/Output) buses is performed at the time of system configuration by writing appropriate values into configuration registers incorporated into each of the interface circuits.

Abstract: There is disclosed a memory control circuit for use in a processing system containing a plurality of processors coupled to a main memory by a common bus. The memory control circuit is adapted for implementing directory-based coherency in the processing system according to a selected coherency algorithm and comprises: 1) monitoring circuitry for detecting coherency corruption in a coherency directory associated with the main memory; and 2) coherency control circuitry responsive to a detection of coherency corruption in the coherency directory for dynamically modifying the selected coherency algorithm, thereby enabling the processing system to shut down in a controlled manner.

Abstract: A method for processing memory requests and a memory controller that implements the method are disclosed. The method includes the steps of (a) receiving a first memory request from a first bus, (b) issuing a first coherency request on a second bus in order to process the first memory request, (c) storing the first coherency request in a storage area of the memory controller that is configured to receive memory requests from the second bus, and (d) processing the first coherency request from the storage area.

Abstract: A multiprocessor computing apparatus including a plurality of processors each having a cache memory and preferably arranged in nodes on a system bus. A first cache coherency providing mechanism coupled to the processors for achieving system level cache coherency. A second cache coherency providing mechanism is also provided. When an error is detected in the first cache coherency providing mechanism, this mechanism is disabled and cache coherency is achieved by the second cache coherency providing mechanism. In a preferred embodiment, the first mechanism includes coherency directories and the second mechanism includes bus snooping.

Abstract: A retry scheme for optimizing use of a first bus in a computer system which includes a plurality of bus masters connected through the first bus to an interface circuit and second bus. The interface circuit includes logic for generating a busy signal when the second bus is in a busy state and logic for generating a retry signal when the interface circuit is addressed by a bus master while the second bus is in a busy state. Each bus master includes logic for receiving the retry signal and relinquishing control of the common bus upon receipt of the retry signal from the interface circuit. A bus arbiter includes logic for receiving the busy signal and preventing any bus master seeking access to the second bus from participating in arbitration for control of the common first bus until the busy signal has been negated. Thus, during the term of the busy signal the first bus may be controlled by any bus master not requiring access to the shared resource.