Abstract: A BiCMOS integrated circuit design having an oversized isolation area surrounding circuit elements which are non-scaleable is provided. The non-scaleable circuit elements can be removed from the layout, and the remaining scaleable elements shrunk by a CAD system. After shrinking the scaleable elements and the isolation area, the non-scaleable elements are returned to the layout at their original size, and located within the scaled-down isolation area.

Abstract: An improved semiconductor die for plastic encapsulated semiconductor devices which impedes the inherent delamination caused by the differing expansion coefficients of the semiconductor die and plastic encapsulation. Topological configurations are processed in the die corners of the semiconductor die which are void of circuitry. The topological configurations act as barriers and slow the delamination progression. This leaves the operational circuitry unaffected for an increased time thereby increasing device lifetime.

Abstract: A deep, buried n.sup.- channel blanket implant beneath both n.sup.- channel and p-channel devices in MOS integrated circuits, whether complementary MOS (CMOS) or not. It is known to use deep, lightly-doped n.sup.- channel implant to improve the characteristics of p-channel (PMOS) devices, although one skilled in the art would expect such an n.sup.- implant to be detrimental to n-channel (NMOS) devices. It has been discovered that such implants not only do not degrade the NMOS devices, but in fact improve their performance, with respect to body effect and junction capacitance.