Abstract: Impedance paths for integrated circuits having microelectromechanical systems (MEMS) switches that allow for electrical charge to bleed from circuit nodes to fixed electric potentials (e.g., ground) are described. Such paths are referred to herein as charge bleed circuits. The circuit nodes may be circuit locations where electrical charge may accumulate because there is no other path for the electrical charge to dissipate. In some embodiments, a charge bleed circuit includes a switchable device (e.g., a MEMS switch, a solid-state device switch, or a circuit including various solid-state device switches that, collectively, implement a device that can be switched on and off) that connects and disconnects the impedance path from a circuit node. This may allow the device to perform different types of measurements at desired performance levels.

Abstract: A photonic integrated circuit and a method for its manufacture are provided. In an embodiment, an intermetal dielectric layer, for example, a silicon oxide layer, is contiguous between an upper metal layer and a lower metal layer on a substrate. One or more waveguides having top and bottom faces are formed in respective waveguide layers within the intermetal dielectric layer between the upper and lower metal layers. There is a distance of at least 600 nm from the upper metal layer to the top face of the uppermost of the several waveguides. There is a distance of at least 600 nm from the lower metal layer to the bottom face of the lowermost of the several waveguides. The waveguides are formed of silicon nitride for longer wavelengths and alumina for shorter wavelengths. These dimensions and materials are favorable for CMOS processing, among other things.

Abstract: A method for generating an integrated circuit layout is disclosed. One embodiment includes receiving an integrated circuit netlist describing a plurality of transistors and a plurality of conductors for interconnecting the plurality of transistors, each of the plurality of transistors having a width in a layout corresponding to the integrated circuit netlist. More than one of the plurality of transistors are determined to be the widest transistors, all having the same width. One of the widest transistors is folded to produce a folded transistor that is electrically equivalent to the widest transistor. The folded transistor has at least two fingers, each finger having a smaller width than the width of the widest transistors. A fold solution for the layout having the one folded transistor is created.

Abstract: A method for generating an integrated circuit layout is disclosed. One embodiment includes receiving an integrated circuit netlist describing a plurality of transistors and a plurality of conductors for interconnecting the plurality of transistors, each of the plurality of transistors having a width in a layout corresponding to the integrated circuit netlist. More than one of the plurality of transistors are determined to be the widest transistors, all having the same width. One of the widest transistors is folded to produce a folded transistor that is electrically equivalent to the widest transistor. The folded transistor has at least two fingers, each finger having a smaller width than the width of the widest transistors. A fold solution for the layout having the one folded transistor is created.

Abstract: This disclosure describes an apparatus for wrapping all exposed surfaces of a large annular coil, including its hollow cylindrical core, to prevent contamination and to prepare it for shipping. A pair of opposing robotic arms hand off or transfer a roll of wrapping material, such as paper or plastic, from a gripper on one arm to a gripper on the other arm. The arms travel around both ends of the coil, handing off the roll back and forth above the coil and in the center of its hollow core, as it is slowly rotated by a variable-speed coil roller. The speed of the coil roller is adjusted such that the wrap overlaps during each successive pass around the coil, thereby ensuring its sealed integrity. A compact variable-tensioning mechanism, inserted into the roll, maintains constant tension on the wrapping material to keep it taut while being pulled around the coil.

Abstract: This invention is related to a novel class of 3-arylpyrimidine ethers and thioethers having insecticidal, miticidal and nematocidal activity at low concentration. The class of compounds is represented by formula (I): ##STR1## wherein R.sup.1, R.sup.2, R.sup.3, R.sup.4, R.sup.5, R.sup.6, R.sup.7, X and Y have the significance given in the description.Pesticidal compositions, methods of controlling pests and methods for preparing the compounds are within the scope of the invention.

Abstract: Pyridine derivatives of substituted thiadiazoleureas exhibit desirable herbicidal and plant growth regulatory properties.

Abstract: A defoliating composition comprising a compound have the structural formula ##STR1## wherein R is F, Cl, 3-Br, 4-Br, I, CN or CX.sub.3, where X is F, Cl or Br; R.sup.1 is hydrogen or C.sub.1 -C.sub.4 alkyl; and R.sup.2 is C.sub.1 -C.sub.4 alkyl and a carrier for said compound is disclosed.