Abstract: A fluid ejection device includes a plurality of fluid actuation devices, a plurality of memory cells, and a configuration register. Each memory cell of the plurality of memory cells corresponds to a fluid actuation device of the plurality of fluid actuation devices. The configuration register stores data to enable or disable access to the plurality of memory cells.

Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes an interface, a digital circuit, an analog circuit, and control logic. The digital circuit outputs a digital signal to the interface. The analog circuit outputs an analog signal to the interface. The control logic activates the digital circuit or the analog circuit.

Abstract: An integrated circuit includes a plurality of memory cells, an address decoder to select memory cells based on a data signal, activation logic to activate selected memory cells based on the data signal and a fire signal, and configuration logic to enable or disable access to the plurality of memory cells.

Abstract: A fluid ejection device includes a plurality of fluid actuation devices, a plurality of memory cells, and a configuration register. Each memory cell of the plurality of memory cells corresponds to a fluid actuation device of the plurality of fluid actuation devices. The configuration register stores data to enable or disable access to the plurality of memory cells.

Abstract: A print component includes an array of fluidic actuation structures including a first column of fluidic actuating structures addressable by a set of actuation addresses, each fluidic actuating structure having a different one of the actuation addresses and having a fluidic architecture type, and a second column of fluidic actuating structures addressable by the set of actuation addresses. Each fluidic actuating structure of the second column has a different one of the actuation addresses and has a same fluidic architecture type as the fluidic actuating structure of the first column having the same address. An address bus communicates the set of addresses to the array of fluidic actuating structures, and a fire signal line communicates a plurality of fire pulse signal types to the array of fluidic actuating structures, the fire pulse signal type depending on the actuation address on the address bus.

Abstract: A fluid ejection device includes a plurality of fluid actuation devices, a plurality of memory cells, and a configuration register. Each memory cell of the plurality of memory cells corresponds to a fluid actuation device of the plurality of fluid actuation devices. The configuration register stores data to enable or disable access to the plurality of memory cells.

Abstract: A print component includes an array of fluidic actuation structures including a first column of fluidic actuating structures addressable by a set of actuation addresses, each fluidic actuating structure having a different one of the actuation addresses and having a fluidic architecture type, and a second column of fluidic actuating structures addressable by the set of actuation addresses. Each fluidic actuating structure of the second column has a different one of the actuation addresses and has a same fluidic architecture type as the fluidic actuating structure of the first column having the same address. An address bus communicates the set of addresses to the array of fluidic actuating structures, and a fire signal line communicates a plurality of fire pulse signal types to the array of fluidic actuating structures, the fire pulse signal type depending on the actuation address on the address bus.

Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes a plurality of first non-volatile memory cells and control logic. Each first non-volatile memory cell stores a customization bit. The control logic configures an operation of the integrated circuit based on the customization bits.

Abstract: An integrated circuit includes thermal tracking logic, control logic, and an output interface. The thermal tracking logic determines a temperature of a fluid ejection die. The control logic defines an emulated parameter of the fluid ejection die as a function of the temperature of the fluid ejection die. The output interface outputs the emulated parameter to a printer system based on the function and the temperature of the fluid ejection die.

Abstract: A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signal paths which communicate operating signals to the print component. The memory circuit includes a controllable selector connected in line with one of the signal paths via the I/O pads, the selector controllable to disconnect the corresponding signal path to the print component, and a memory component to store memory values associated with the print component. A control circuit, in response to a sequence of operating signals received by the I/O pads representing a memory read, to operate the controllable selector to disconnect the signal path to the print component to block the memory read of the print component, and provide an analog signal to the analog pad to provide an analog electrical value at the analog pad representing stored memory values selected by the memory read.

Abstract: A communicating print component a print head comprising a number of memory bits and a single lane analog bus conductively coupling the number of memory bits to a pad located on the exterior of the print head. The pad is to transmit an electrical signal from the number of memory bits, wherein the electrical signal indicates a combination of all selected bits of the number of memory bits.

Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes a status register, a plurality of interfaces, and control logic. The plurality of interfaces include a mode interface, a data interface, and a fire interface. The control logic enables reading of the status register in response to a signal on the mode interface transitioning to logic high with a logic high signal on the data interface, and transitioning a signal on the fire interface to logic high with the signal on the single data interface floating.

Abstract: A fluid ejection device includes a plurality of fluid actuation devices, a plurality of memory cells, and a configuration register. Each memory cell of the plurality of memory cells corresponds to a fluid actuation device of the plurality of fluid actuation devices. The configuration register stores data to enable or disable access to the plurality of memory cells.

Abstract: In some examples, a fluid dispensing device component includes a plurality of fluidic dies each comprising a memory, a plurality of control inputs to provide respective control information to respective fluidic dies of the plurality of fluidic dies, and a data bus connected to the plurality of fluidic dies, the data bus to provide data of the memories of the plurality of fluidic dies to an output of the fluid dispensing device component.

Abstract: A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signals paths which communicate operating signals to the print component, and a memory component to store memory values associated with the print component. A control circuit to, in response to identifying a sequence of operating signals representing a memory read, provide a first analog signal on the analog pad in parallel with a second analog signal from the print component to provide an analog electrical value on the analog pad representing stored memory values selected by the memory read.

Abstract: A communicating print component a print head comprising a number of memory bits and a single lane analog bus conductively coupling the number of memory bits to a pad located on the exterior of the print head. The pad is to transmit an electrical signal from the number of memory bits, wherein the electrical signal indicates a combination of all selected bits of the number of memory bits.

Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes a plurality of contact pads, a plurality of pulldown devices, and control logic. The plurality of contact pads include a first contact pad and a second contact pad. Each of the pulldown devices is electrically coupled to a corresponding contact pad. The control logic enables at least a portion of the pulldown devices in response to both a logic low signal on the first contact pad and a logic low signal on the second contact pad.

Abstract: A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signal paths which communicate operating signals to the print component. The memory circuit includes a controllable selector connected in line with one of the signal paths via the I/O pads, the selector controllable to disconnect the corresponding signal path to the print component, and a memory component to store memory values associated with the print component. A control circuit, in response to a sequence of operating signals received by the I/O pads representing a memory read, to operate the controllable selector to disconnect the signal path to the print component to block the memory read of the print component, and provide an analog signal to the analog pad to provide an analog electrical value at the analog pad representing stored memory values selected by the memory read.

Abstract: A die for a printhead is provided in examples. The die includes a number of fluidic actuator arrays. A data block is associated with each of the plurality of fluidic actuator arrays. The die includes an interface comprising a data pad and a clock pad, wherein a data bit value present at the data pad is loaded into a first data block corresponding to a first fluidic actuator array on a rising clock edge and loaded into a second data block corresponding to a second fluidic actuator array on a falling clock edge.

Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes a configuration register, a plurality of interfaces, and control logic. The plurality of interfaces include a mode interface and a data interface. The control logic enables writing to the configuration register in response to a signal on the mode interface transitioning to logic high with a logic high signal on the data interface.