Abstract: A monitor for monitoring the occurrence of events on the bus (15) of a multiprocessor computer system. The bus event monitor (BEM) includes a dedicated BEM processor (23) and an event counter subsystem (25). During each bus cycle, the BEM (21) captures and interprets the packet of data being transmitted on the bus (15). If the packet represents an event designated by the user to be of interest, a counter associated with the type of packet that was captured and interpreted is incremented by one. More specifically, a field programmable gate array (FPGA), configured by the user, defines the type of events to be counted. When an event to be accounted occurs, the FPGA (33) produces a counter address that is based on the nature of the event, and causes an enable pulse to be generated. The address is applied to the active one of two event counter banks (39a, 39b) via an input crossbar switch (37a). The enable pulse enables the addressed event counter to be incremented by one.

Abstract: A method and apparatus for optimizing the performance of a multibus data processing system is provided. An I/O controller is coupled to the I/O bus and includes MORE bit setting means for initiating a MORE stream transaction on the I/O bus and for thereafter terminating the MORE stream transaction. An adapter coupling the I/O bus to the system bus, is configured to receive the MORE stream transaction and transfer it to main memory. The adapter includes MORE bit decoding means for identifying the beginning and the end of the MORE stream transaction, and for identifying whether the MORE stream transaction is a READ or WRITE transaction. The adapter also includes a first buffer for receiving data from the I/O bus and transferring the data to the memory in accordance with the memory's full block transfer size, and a second buffer for receiving a full block of data and transferring that data in accordance with the I/O bus transaction limitations.

Abstract: Method and apparatus for high speed parallel transfer of bursts of data between a device and an external interface bus. A burst mode asynchronous protocol is utilized, in which synchronous bursts of data using DATA VALID signals are followed by an asynchronous handshake using an ACKNOWLEDGE signal. The apparatus includes a burst register for storing and transmitting the data words in a burst, and control logic responsive to DATA VALID and ACKNOWLEDGE signals and providing control signals to operate the burst register.