Abstract: A loop buffer is provided with a main store 26 and an auxiliary store 28. The main store 26 stores micro-operation instructions. The auxiliary store 28 has fewer entries than the main store 26 and stores target addresses for predicted taken branch instructions stored within the main store 26. Read control circuitry serves to control reading from the main store and from an auxiliary store such that target addresses are read from the auxiliary store in association with the predicted taken branch instructions read from the main store.

Abstract: An out-of-order processor 4 groups program instructions together to control their commitment to complete processing. If an instruction within a group has a source operand dependent upon a plurality of destination operands of other instructions then this is identified as a size mismatch hazard. When the program instruction having the size mismatch hazard reaches a commit point within the processor, then it is flushed together with any speculatively executed succeeding program instructions. Furthermore, the group of program instructions containing the program instruction containing the program instruction having the size mismatch is divided into a plurality of groups of program instructions each containing a single program instruction which are then replayed through the processing mechanisms.

Abstract: A processor 2 for performing out-of-order execution of a stream of program instructions includes a special register access pipeline for performing status access instructions accessing a status register 20. In order to serialise these status access instructions relative to other instructions within the system access timing control circuitry 32 permits dispatch of other instructions to proceed but controls the commit queue and the result queue such that no program instructions in program order succeeding the status access instruction are permitted to complete until after a trigger state has been detected in which all program instructions preceding in program order the status access instruction have been performed and made any updates to the architectural state. This is followed by the performance of the status access instruction itself.

Abstract: A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.

Abstract: A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being written thereto. Instead of adding these zero values everywhere in the data path, they are instead represented by zero flags in at least the physical registers utilized for register renaming operations and in the result queue prior to results being written to the architectural register file. This saves circuitry resources and reduces energy consumption.

Abstract: A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.

Abstract: A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.

Abstract: A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being written thereto. Instead of adding these zero values everywhere in the data path, they are instead represented by zero flags in at least the physical registers utilised for register renaming operations and in the result queue prior to results being written to the architectural register file. This saves circuitry resources and reduces energy consumption.

Abstract: An out-of-order renaming processor is provided with a register file within which aliasing between registers of different sizes may occur. In this way a program instruction having a source register of a double precision size may alias with two single precision registers being used as destinations of one or more preceding program instructions. In order to track this data dependency the double precision register may be remapped into a micro-operation specifying two single precision registers as its source register. In this way, scheduling circuitry may use its existing hazard detection and management mechanisms to handle potential data hazards and dependencies. Not all program instructions having such data hazards between registers of different sizes are handled by this source register remapping. For these other program instructions a slower mechanism for dealing with the data dependency hazard is provided.

Abstract: A processor 2 supporting register renaming has a rename table 20 in which the flag register has multiple tag values associated therewith. These tag values indicate which virtual register corresponds to a destination flag register of the oldest instruction which wrote a still up-to-date value of a subset of the flags.

Abstract: A processor is disclosed having a plurality of general purpose registers for storing data for processing by the processor; a set of system configuration registers for storing data indicative of a current configuration of the processor; the system configuration registers being located together in a register file; and at least some of the set of system configuration registers having a shadow register for storing a duplicate value remote from the register file, the shadow register being located close to a component that the shadow register stores a configuration value for.

Abstract: A processor 2 for performing out-of-order execution of a stream of program instructions includes a special register access pipeline for performing status access instructions accessing a status register 20. In order to serialise these status access instructions relative to other instructions within the system access timing control circuitry 32 permits dispatch of other instructions to proceed but controls the commit queue and the result queue such that no program instructions in program order succeeding the status access instruction are permitted to complete until after a trigger state has been detected in which all program instructions preceding in program order the status access instruction have been performed and made any updates to the architectural state. This is followed by the performance of the status access instruction itself.

Abstract: An out-of-order processor 4 groups program instructions together to control their commitment to complete processing. If an instruction within a group has a source operand dependent upon a plurality of destination operands of other instructions then this is identified as a size mismatch hazard. When the program instruction having the size mismatch hazard reaches a commit point within the processor, then it is flushed together with any speculatively executed succeeding program instructions. Furthermore, the group of program instructions containing the program instruction containing the program instruction having the size mismatch is divided into a plurality of groups of program instructions each containing a single program instruction which are then replayed through the processing mechanisms.

Abstract: A processor 2 includes instruction decoding circuitry 8 and processing circuitry 16, 18, 20, 22, 24. The instruction decoding circuitry decodes at least one conditional program instruction in accordance with a conditional prediction as one of, in accordance with the condition prediction being a condition pass, one or more micro-operation instructions that control the processing circuitry to perform the processing action together with a condition resolution micro-operation instruction, or in accordance with the condition prediction being a condition fail, at least a condition resolution micro-operation instruction. Condition resolution circuitry 24 responds to the condition resolution micro-operation instruction to determine if the condition prediction is incorrect.

Abstract: A loop buffer is provided with a main store 26 and an auxiliary store 28. The main store 26 stores micro-operation instructions. The auxiliary store 28 has fewer entries than the main store 26 and stores target addresses for predicted taken branch instructions stored within the main store 26. Read control circuitry serves to control reading from the main store and from an auxiliary store such that target addresses are read from the auxiliary store in association with the predicted taken branch instructions read from the main store.

Abstract: A method of instruction issue (3200) in a microprocessor (1100, 1400, or 1500) with execution pipestages (E1, E2, etc.) and that executes a producer instruction Ip and issues a candidate instruction I0 (3245) having a source operand dependency on a destination operand of instruction Ip. The method includes issuing the candidate instruction I0 as a function (1720, 1950, 1958, 3235) of a pipestage EN(I0) of first need by the candidate instruction for the source operand, a pipestage EA(Ip) of first availability of the destination operand from the producer instruction, and the one execution pipestage E(Ip) currently associated with the producer instruction. A method of data forwarding (3300) in a microprocessor (1100, 1400, or 1500) having a pipeline (1640) having pipestages (E1, E2, etc.

Abstract: A processor is disclosed having a plurality of general purpose registers for storing data for processing by the processor; a set of system configuration registers for storing data indicative of a current configuration of the processor; the system configuration registers being located together in a register file; and at least some of the set of system configuration registers having a shadow register for storing a duplicate value remote from the register file, the shadow register being located close to a component that the shadow register stores a configuration value for.

Abstract: An out-of-order renaming processor is provided with a register file within which aliasing between registers of different sizes may occur. In this way a program instruction having a source register of a double precision size may alias with two single precision registers being used as destinations of one or more preceding program instructions. In order to track this data dependency the double precision register may be remapped into a micro-operation specifying two single precision registers as its source register. In this way, scheduling circuitry may use its existing hazard detection and management mechanisms to handle potential data hazards and dependencies. Not all program instructions having such data hazards between registers of different sizes are handled by this source register remapping. For these other program instructions a slower mechanism for dealing with the data dependency hazard is provided.

Abstract: A processor 2 supporting register renaming has a rename table 20 in which the flag register has multiple tag values associated therewith. These tag values indicate which virtual register corresponds to a destination flag register of the oldest instruction which wrote a still up-to-date value of a subset of the flags.

Abstract: A bus interface apparatus and method are implemented. A pair of data streams is generated from the stream of data to be launched onto a data bus. Each stream is staged along a corresponding data path that includes a plurality of storage elements. Each path feeds an input of a multiplexer (MUX). The output of the MUX drives the bus, and the MUX selects a data value for launching onto the bus in response to a signal derived from an internal bus clock. The internal bus clock is also used to generate a bus clock that is output to the bus along with the data. The period of the bus clock may be a preselected multiple of the period of a processor clock. The data is staged along the two data streams in response to clocking signals derived from the processor clock. Each of the clocking signals is qualified by a corresponding hold signal, that, when asserted, holds the clocking signals in a predetermined state.