Abstract: A bus interface apparatus and method are implemented. A pair of data streams is generated from the stream of data to be launched onto a data bus. Each stream is staged along a corresponding data path that includes a plurality of storage elements. Each path feeds an input of a multiplexer (MUX). The output of the MUX drives the bus, and the MUX selects a data value for launching onto the bus in response to a signal derived from an internal bus clock. The internal bus clock is also used to generate a bus clock that is output to the bus along with the data. The period of the bus clock may be a preselected multiple of the period of a processor clock. The data is staged along the two data streams in response to clocking signals derived from the processor clock. Each of the clocking signals is qualified by a corresponding hold signal, that, when asserted, holds the clocking signals in a predetermined state.

Abstract: A bus-clock-speed-independent apparatus and method of wrap input/output (I/O) testing of an I/O interface is provided. Launch data is launched in response to a launch clock. A capture clock is derived from the launch clock by delaying the launch clock through a programmable delay. Launch data is wrapped through the I/O interface buffers and captured in response to the capture clock. A initial value of the programmable delay is selected and successively increased or decreased until the launch data is just captured, or just fails to be captured, respectively. The value of the programmable delay when this occurs provides a measure of the limiting speed of the I/O interface.

Abstract: The present invention provides a method and apparatus for allowing autonomous, way specific tag updates. More specifically, the invention provides way specific tag and status updates while concurrently allowing reads of the ways not currently being updated. If a read hit is determined, then the read is processed in a typical fashion. However, if the read is a read miss and one of the ways is flagged as being updated, then all ways are read again once the specific way has completed its updated.

Abstract: Where a plurality of ordered transactions are received for data transfers on a pipelined bus, each transaction in the series is initiated before all prospective retry responses to the preceding ordered transactions may be asserted. The address responses to all preceding ordered transfers are then monitored in connection with performance of the newly initiated transfer. If a retry response to any preceding ordered transaction is asserted, a self-initiated retry response for all subsequent transactions, including the newly initiated transfer, is also asserted. The system-retried transactions and all succeeding, ordered transactions are immediately reattempted. The overlapping performance of the ordered transfers reduces the latency of non-retried transfers, achieving performance comparable to non-ordered transactions.

Abstract: The present invention provides a method and apparatus for optimizing bus utilization while maintaining read and write coherence. More specifically the invention provides bus utilization optimization by prioritizing read transactions before write transactions, where there is no collision pending. When a collision pending is determined, then the read and write transactions are processed according to the age of the transaction(s) allowing for data coherency.

Abstract: A data processing system includes at least a first processor and a second processor that each have a respective translation lookaside buffer (TLB). In response to detection by the second processor of a TLB entry invalidation request, the second processor marks at least one memory referent instruction that is being processed by the second processor and invalidates a TLB entry in the TLB of the second processor. In response to receipt of a synchronization request at the second processor, the second processor indicates to the first processor that the second processor has invalidated the TLB entry if the second processor has completed processing the marked instruction. During the interval between receipt of the synchronization request and indicating to the first processor that the second processor has invalidated the TLB entry, the second processor continues to process instructions, including fetching instructions for processing.

Abstract: To implement full gathering of data transfers from a processor to a system bus without adding many levels of logic to the write enable logic for transaction queue entries or reducing the processor operating frequency, gatherable combinations are divided and gathering is performed in multiple stages operating in parallel. During the first stage, a subset of the full gathering is performed between incoming transactions and the last transaction received, coalescing the two transfers into a single transaction entry if one of the possible combinations within the subset is satisfied. During the second stage, existing queue entries are tested for the remainder of the full gather combination set and merged if a combination within the remaining subset is satisfied.