Abstract: A method is provided for cabling a plurality of hardware components. A chassis controller establishes a wireless connection to a wireless device. The chassis controller, via a wireless interface, transmits a chassis map to the wireless device over the wireless connection. The chassis controller, via the wireless interface, transmits to the wireless device, an indication of a first port to be cabled over the wireless connection, the first port. The first port is of a first hardware component of the plurality of hardware components. The chassis controller tests the first port to determine whether cabling of the first port has been performed correctly.

Abstract: The present invention encompasses polyurethane adhesive compositions comprising aliphatic polycarbonate chains. In one aspect, the present invention encompasses polyurethane adhesives derived from aliphatic polycarbonate polyols and polyisocyanates wherein the polyol chains contain a primary repeating unit having a structure: In another aspect, the invention provides articles comprising the inventive polyurethane compositions as well as methods of making such compositions.

Abstract: A data storage system includes a plurality of storage devices forming a storage array for storing data and associated error correction codes and a controller coupled to the plurality of storage devices. The controller is configured to, responsive to an error in a data element among the data, rebuild the data element from other data elements and an error correction code in the storage array and overwrite the error correction code with the rebuilt data element.

Abstract: A data storage system includes a plurality of storage devices forming a storage array for storing data and associated error correction codes and a controller coupled to the plurality of storage devices. The controller is configured to, responsive to an error in a data element among the data, rebuild the data element from other data elements and an error correction code in the storage array and overwrite the error correction code with the rebuilt data element.

Abstract: Embodiments relate to a computer for transmitting data in a network. The computer includes at least one data transmission port configured to be connected to at least one storage device via a plurality of paths of a network. The computer further includes a processor configured to detect recurring intermittent errors in one or more paths of the plurality of paths and to disable access to the one or more paths based on detecting the recurring intermittent errors.

Abstract: A memory and a method of storing data in a memory are provided. The memory comprises a memory block comprising data bits and additional bits. The memory includes logic which, when receiving a first command, writes data into the data bits of the memory block, wherein the data is masked according to a first input. The logic, in response to a second command, writes data into the data bits of the memory block and writes a second input into the additional bits of the memory block.

Abstract: Embodiments relate to a computer for transmitting data in a network. The computer includes at least one data transmission port configured to be connected to at least one storage device via a plurality of paths of a network. The computer further includes a processor configured to detect recurring intermittent errors in one or more paths of the plurality of paths and to disable access to the one or more paths based on detecting the recurring intermittent errors.

Abstract: Effects of a physical memory fault are mitigated. In one example, to facilitate mitigation, memory is allocated to processing entities of a computing environment, such as applications, operating systems, or virtual machines, in a manner that minimizes impact to the computing environment in the event of a memory failure. Allocation includes using memory structure information, including, information regarding fault containment zones, to allocate memory to the processing entities. By allocating memory based on fault containment zones, a fault only affects a minimum number of processing entities.

Abstract: A memory and a method of storing data in a memory are provided. The memory comprises a memory block comprising data bits and additional bits. The memory includes logic which, when receiving a first command, writes data into the data bits of the memory block, wherein the data is masked according to a first input. The logic, in response to a second command, writes data into the data bits of the memory block and writes a second input into the additional bits of the memory block.

Abstract: Techniques are disclosed for managing inventory data for components of a server system. In one embodiment, a global management controller is provided, that is operatively connected to a plurality of local management controllers. Each local management controller is configured to manage a subset of the components of the server system. Each local management controller is also configured to generate, for each component, a checksum based on vital product data (VPD) of the component. Each local management controller is also configured to compute a composite checksum based on the checksums generated for the components in the subset. The global management controller is configured to maintain a global view of the VPD in the computer system, based on the checksums and/or composite checksums.

Abstract: A power plant control system determines an augmented operating parameter set point responsive to a life cycle cost (LCC) objective function responsive to a LCC model. The augmented operating parameter value may be responsive to an initial set point determined by a controls model and a performance indicator determined by a performance model. The power plant may include a thermal generator, such as a gas turbine or other fuel-burning generator, and the operating parameter may include firing temperature, fuel flow rate, steam pressure/temperature/flow rate, and/or another suitable operating parameter. An offer curve is generated responsive to the augmented operating parameter.

Abstract: Effects of a physical memory fault are mitigated. In one example, to facilitate mitigation, memory is allocated to processing entities of a computing environment, such as applications, operating systems, or virtual machines, in a manner that minimizes impact to the computing environment in the event of a memory failure. Allocation includes using memory structure information, including, information regarding fault containment zones, to allocate memory to the processing entities. By allocating memory based on fault containment zones, a fault only affects a minimum number of processing entities.

Abstract: A data processing device is provided that facilitates cache coherence policies. In one embodiment, a data processing device utilizes invalidation tags in connection with a cache that is associated with a processing engine. In some embodiments, the cache is configured to store a plurality of cache entries where each cache entry includes a cache line configured to store data and a corresponding cache tag configured to store address information associated with data stored in the cache line. Such address information includes invalidation flags with respect to addresses stored in the cache tags. Each cache tag is associated with an invalidation tag configured to store information related to invalidation commands of addresses stored in the cache tag. In such embodiment, the cache is configured to set invalidation flags of cache tags based upon information stored in respective invalidation tags.

Abstract: The present invention encompasses polyurethane adhesive compositions comprising aliphatic polycarbonate chains. In one aspect, the present invention encompasses polyurethane adhesives derived from aliphatic polycarbonate polyols and polyisocyanates wherein the polyol chains contain a primary repeating unit having a structure. In another aspect, the invention provides articles comprising the inventive polyurethane compositions as well as methods of making such compositions.

Abstract: A method is provided for cabling a plurality of hardware components. A chassis controller establishes a wireless connection to a wireless device. The chassis controller, via a wireless interface, transmits a chassis map to the wireless device over the wireless connection. The chassis controller, via the wireless interface, transmits to the wireless device, an indication of a first port to be cabled over the wireless connection, the first port. The first port is of a first hardware component of the plurality of hardware components. The chassis controller tests the first port to determine whether cabling of the first port has been performed correctly.

Abstract: Techniques are disclosed for managing a switch fabric. In one embodiment, a server system is provided that includes a midplane, one or more server cards, switch modules and a management controller. The midplane may include a fabric interconnect for a switch fabric. The one or more server cards and the switch modules may be operatively connected to the midplane. The switch modules may be configured to switch network traffic for the one or more server cards. The management controller may be configured to manage the switch modules via the fabric interconnect.

Abstract: A method is provided for cabling a plurality of hardware components. A chassis controller establishes a wireless connection to a wireless device. The chassis controller, via a wireless interface, transmits a chassis map to the wireless device over the wireless connection. The chassis controller, via the wireless interface, transmits to the wireless device, an indication of a first port to be cabled over the wireless connection, the first port. The first port is of a first hardware component of the plurality of hardware components. The chassis controller tests the first port to determine whether cabling of the first port has been performed correctly.

Abstract: A data processing device is provided that includes an array of working memory banks and an associated processing engine. The working memory bank array is configured with at least one independently activatable memory bank. A dirty data counter (DDC) is associated with the independently activatable memory bank and is configured to reflect a count of dirty data migrated from the independently activatable memory bank upon selective deactivation of the independently activatable memory bank. The DDC is configured to selectively decrement the count of dirty data upon the reactivation of the independently activatable memory bank in connection with a transient state. In the transient state, each dirty data access by the processing engine to the reactivated memory bank is also conducted with respect to another memory bank of the array. Upon a condition that dirty data is found in the other memory bank, the count of dirty data is decremented.

Abstract: Techniques are disclosed for managing inventory data for components of a server system. In one embodiment, a global management controller is provided, that is operatively connected to a plurality of local management controllers. Each local management controller is configured to manage a subset of the components of the server system. Each local management controller is also configured to generate, for each component, a checksum based on vital product data (VPD) of the component. Each local management controller is also configured to compute a composite checksum based on the checksums generated for the components in the subset. The global management controller is configured to maintain a global view of the VPD in the computer system, based on the checksums and/or composite checksums.

Abstract: Techniques are disclosed for reducing impact of a repair action in a switch fabric. In one embodiment, a server system is provided that includes a first interposer card that operatively connects one or more server cards to a midplane. The first interposer card may include a switch module that switches network traffic for the one or more server cards. The first interposer card may be hot-swappable from the midplane, and the one or more server cards may be hot-swappable from the first interposer card.