Patents by Inventor James Oakes

James Oakes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110170226
    Abstract: An embodiment of a tunable capacitor can include a plurality of capacitors connected in series where at least two capacitors of the plurality of capacitors share a common electrode where the at least two capacitors are in lateral proximity and a bias that is capable of being applied to the at least two capacitors whereby the at least two capacitors vibrate in opposite phase to each other when the bias and an RF signal is applied to the at least two capacitors.
    Type: Application
    Filed: March 23, 2011
    Publication date: July 14, 2011
    Applicant: PARATEK MICROWAVE, INC.
    Inventors: James Oakes, James Martin, Andrey Kozyrev, A. Prudan
  • Patent number: 7936553
    Abstract: An embodiment of the present invention provides a device, comprising a multilayered tunable dielectric capacitor, wherein said multilayers of tunable dielectric are adapted to be DC biased to reduce the dielectric constant; and wherein the DC bias is arranged so that the number of layers of tunable dielectric biased positively is equal to the number of layers of tunable dielectric biased negatively.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: May 3, 2011
    Assignee: Paratek Microwave, Inc.
    Inventors: James Oakes, James Martin, Andrey Kozyrev, Alexandr Prudan
  • Publication number: 20090040687
    Abstract: An embodiment of the present invention provides a method, comprising reducing the losses due to electro-mechanical coupling and improving Q in a multilayered capacitor by placing a first capacitor layer adjacent at least one additional capacitor layer and sharing a common electrode in between the two such that the acoustic vibration of the first layer is coupled to an anti-phase acoustic vibration of the at least one additional layer.
    Type: Application
    Filed: August 8, 2007
    Publication date: February 12, 2009
    Inventors: James Oakes, James Martin
  • Publication number: 20080232023
    Abstract: An embodiment of the present invention provides a device, comprising a multilayered tunable dielectric capacitor, wherein said multilayers of tunable dielectric are adapted to be DC biased to reduce the dielectric constant; and wherein the DC bias is arranged so that the number of layers of tunable dielectric biased positively is equal to the number of layers of tunable dielectric biased negatively.
    Type: Application
    Filed: March 22, 2007
    Publication date: September 25, 2008
    Inventors: James Oakes, James Martin, Andrey Kozyrev, A. Prudan
  • Publication number: 20070152773
    Abstract: At least an embodiment of the present technology provides a capacitor, comprising a substrate, a first solid electrode disposed on the substrate, a second electrode broken into subsections, the subsections connected by a bus line and separated from the first electric by a dielectric medium. The second electrode broken into subsections may have a lower resistance than the first solid electrode and by changing the width and length of the sides of the subsections, the resistance of the first electrode is modifiable.
    Type: Application
    Filed: November 20, 2006
    Publication date: July 5, 2007
    Inventors: James Oakes, James Martin
  • Publication number: 20070017160
    Abstract: Certain non-limiting embodiments of the present disclosure comprise a family of composite materials targeting specific applications through a materials design approach involving; 1) a hard particulate; 2) a carrier or binder phase; and 3) one or more additives for property enhancement and/or hardness adjustment. According to certain embodiments, the composite material may be one of flexible conformal sheet; a rigid machinable molded preform; and an extrudable putty. Methods of manufacture of the composite materials are also disclosed.
    Type: Application
    Filed: July 20, 2006
    Publication date: January 25, 2007
    Inventors: Steven Caldwell, James Oakes
  • Publication number: 20070007854
    Abstract: An embodiment of the present invention provides an apparatus, comprising a voltage tunable capacitor including a substrate, wherein a surface of the substrate opposite the voltage tunable capacitor is made physically rough such that reflections off a surface internal to the substrate are scattered and dissipated. The surface of the substrate opposite the voltage tunable capacitor may be made physically rough by using abrasion or other mechanical techniques or may be made physically rough by creating a rough surface through deposition of a material on the surface in a non-uniform manner such as evaporating a rough metal or dielectric. Further, the surface of the substrate opposite the voltage tunable capacitor may be made physically rough by plating metals under what would otherwise be considered a poor plating condition leading to a rough surface.
    Type: Application
    Filed: October 7, 2005
    Publication date: January 11, 2007
    Inventors: James Oakes, Nicolaas Du Toit, Louise Sengupta, Richard Eden
  • Publication number: 20060237750
    Abstract: An embodiment of the present invention provides a structure comprising a field effect transistor (FET) comprising: at least one source rail with at least one source finger; at least one drain rail with at least one drain finger; and at least one serpentine gate having a plurality of gate fingers, said serpentine gate serpentining between said at least one source finger and said at least one drain finger; and at least one feedforward capacitor symmetrically coupled with said FET via at least one gate rail.
    Type: Application
    Filed: June 19, 2006
    Publication date: October 26, 2006
    Inventors: James Oakes, Vincent Pelliccia
  • Publication number: 20060214165
    Abstract: An apparatus, comprising an integrated circuit, wherein a first portion of the integrated circuit is placed on a first substrate and a second portion of the integrated circuit is placed on a second substrate stacked adjacent the first substrate and wherein the first portion and the second portion of the integrated circuit are interconnected.
    Type: Application
    Filed: February 14, 2006
    Publication date: September 28, 2006
    Inventors: William Macropoulos, Greg Mendolia, James Oakes, Izz Khayo
  • Publication number: 20050247491
    Abstract: The present invention relates to compositions and methods for forming a bit body for an earth-boring bit. The bit body may comprise hard particles, wherein the hard particles comprise at least one carbide, nitride, boride, and oxide and solid solutions thereof, and a binder binding together the hard particles. The binder may comprise at least one metal selected from cobalt, nickel, and iron, and, optionally, at least one melting point reducing constituent selected from a transition metal carbide in the range of 30 to 60 weight percent, boron up to 10 weight percent, silicon up to 20 weight percent, chromium up to 20 weight percent, and manganese up to 25 weight percent, wherein the weight percentages are based on the total weight of the binder.
    Type: Application
    Filed: April 28, 2005
    Publication date: November 10, 2005
    Inventors: Prakash Mirchandani, Jimmy Eason, James Oakes, James Westhoff, Gabriel Collins, John Stevens, Steven Caldwell, Alfred Mosco
  • Publication number: 20050211475
    Abstract: The present invention relates to compositions and methods for forming a bit body for an earth-boring bit. The bit body may comprise hard particles, wherein the hard particles comprise at least one carbide, nitride, boride, and oxide and solid solutions thereof, and a binder binding together the hard particles. The binder may comprise at least one metal selected from cobalt, nickel, and iron, and at least one melting point reducing constituent selected from a transition metal carbide in the range of 30 to 60 weight percent, boron up to 10 weight percent, silicon up to 20 weight percent, chromium up to 20 weight percent, and manganese up to 25 weight percent, wherein the weight percentages are based on the total weight of the binder.
    Type: Application
    Filed: May 18, 2004
    Publication date: September 29, 2005
    Inventors: Prakash Mirchandani, Jimmy Eason, James Oakes, James Westhoff, Gabriel Collins
  • Publication number: 20050190011
    Abstract: An embodiment of the present invention provides a method of directional coupling, comprising utilizing the phase shift inherent in existing networks within an RF circuit to be monitored; and associating a plurality of capacitors and at least one termination resister with said RF circuit to enable said directional coupling. The plurality of capacitors may be three and said at least one termination resister may be one. In an embodiment of the present invention the RF circuit may be an impedance matching network or a filter.
    Type: Application
    Filed: December 15, 2004
    Publication date: September 1, 2005
    Inventors: James Martin, Simon Gay, James Oakes
  • Publication number: 20050116257
    Abstract: A structure comprising a field effect transistor (FET) comprising at least one source rail with at least one source finger, at least one drain rail with at least one drain finger, and at least one serpentine gate having a plurality of gate fingers, said serpentine gate serpentining between said at least one source finger and said at least one drain finger; and at least one feedforward capacitor asymmetrically coupled with said FET via at least one gate rail. The serpentine gate may include first and second ends that are open at one end or closed at one end and the serpentine gate may include first and second ends that are connected to the at least one gate rail. The structure of one embodiment of the present invention may further include the FET being serially connected with at least one additional FET.
    Type: Application
    Filed: June 21, 2004
    Publication date: June 2, 2005
    Inventors: James Oakes, Vincent Pelliccia
  • Publication number: 20050003238
    Abstract: A cutting tool insert comprises a hard metal substrate having at least two wear-resistant coatings including an exterior ceramic coating and a coating under the ceramic coating being a metal carbonitride having a nitrogen to carbon atomic ratio between 0.7 and 0.95 which causes the metal carbonitride to form projections into the ceramic coating improving adherence and crater resistance of the ceramic coating. Also disclosed is a cutting tool insert including a hard substrate and at least first and second coatings on at least a portion of said substrate. The first coating is of at least about 2 microns, is in contact with the substrate, and includes at least one of a metal carbide, a metal nitride, and a metal carbonitride of a metal selected from the group consisting of zirconium and hafnium. The second coating may include at least one of a metal carbide, a metal nitride, and a metal oxide of a metal selected from groups IIIA, IVB, VB, and VIB of the periodic table.
    Type: Application
    Filed: January 26, 2004
    Publication date: January 6, 2005
    Inventors: Roy Leverenz, John Bost, James Oakes