Abstract: A phase-locked loop includes a voltage-controlled oscillator and a charge-pump loop filter. The voltage-controlled oscillator includes a varactor having a first set of capacitor cells configured to adjust a capacitance based on a first control voltage, and a second set of capacitor cells configured to adjust a capacitance based on a second control voltage. The charge-pump loop filter receives a first and a second update signal, each having at least one state based on a phase difference between a first clock and a second clock, and comprises a first component and a second component. The first component is configured to adjust, during an update period, a voltage across an impedance from a reference level based on the states of the first and second update signals and to return the voltage across the impedance to the reference level prior to an end of the update period, wherein the voltage across the impedance comprises the first control voltage.

Abstract: In one embodiment, the present invention provides a phase-locked loop comprising a charge-pump loop filter and a phase detector system. The charge-pump loop filter is configured to provide a control voltage having a voltage level based on a state of a first control signal and on a state of a second control signal. The phase detector system is configured to receive a first clock, a second clock, and a control signal defining a plurality of states including a first state and a second state. The phase detector system is further configured to provide the first control signal and the second control signal each having a state based on a phase difference between the first and second clocks when the control signal has the first state, and to provide the first control signal and second control signal each having a state asynchronously controlled by the control signal when the control signal has the second state.

Abstract: A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.

Abstract: A method and apparatus for processing a signal is presented. An accumulator receives an input signal and generates an accumulated value. A hysteresis controller sets an adjustable upper and lower limit. The upper and lower limits are compared with the accumulated value in a comparator. The comparator outputs a result, which is fed back into the hysteresis controller through a feedback loop. Once the input signal stays within the upper and lower limits, a test signal is considered within specification. When the input signal is outside of the boundary limits, a corrupt test signal is detected.

Abstract: A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.

Abstract: A method and apparatus for processing a signal is presented. An accumulator receives an input signal and generates an accumulated value. A hysteresis controller sets an adjustable upper and lower limit. The upper and lower limits are compared with the accumulated value in a comparator. The comparator outputs a result, which is fed back into the hysteresis controller through a feedback loop. Once the input signal stays within the upper and lower limits, a test signal is considered within specification. When the input signal is outside of the boundary limits, a corrupt test signal is detected.

Abstract: A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.

Abstract: A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.

Abstract: The addition of an array of transistors through areas of the circuit where active devices normally don't exist, such as under routing channels. By connecting this array of transistors such that the gates are tied to one power supply and the sources and drains to another, the transistors act as bypass capacitors between the power supplies and act to reduce noise on the supplies. Also, the transistors may later be reconnected through changes in the design to form diodes, inverters, buffers, or other logic gates to allow changes to the circuit late in the design cycle.